1 /* 2 * (C) Copyright 2010-2012 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef __TEGRA20_COMMON_H 25 #define __TEGRA20_COMMON_H 26 #include <asm/sizes.h> 27 28 /* 29 * QUOTE(m) will evaluate to a string version of the value of the macro m 30 * passed in. The extra level of indirection here is to first evaluate the 31 * macro m before applying the quoting operator. 32 */ 33 #define QUOTE_(m) #m 34 #define QUOTE(m) QUOTE_(m) 35 36 /* 37 * High Level Configuration Options 38 */ 39 #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ 40 #define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */ 41 #define CONFIG_TEGRA /* which is a Tegra generic machine */ 42 #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ 43 44 #define CONFIG_SYS_CACHELINE_SIZE 32 45 46 #include <asm/arch/tegra20.h> /* get chip and board defs */ 47 48 /* 49 * Display CPU and Board information 50 */ 51 #define CONFIG_DISPLAY_CPUINFO 52 #define CONFIG_DISPLAY_BOARDINFO 53 54 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 55 #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ 56 57 #ifdef CONFIG_TEGRA20_LP0 58 #define TEGRA_LP0_ADDR 0x1C406000 59 #define TEGRA_LP0_SIZE 0x2000 60 #define TEGRA_LP0_VEC \ 61 "lp0_vec=" QUOTE(TEGRA_LP0_SIZE) "@" QUOTE(TEGRA_LP0_ADDR) " " 62 #else 63 #define TEGRA_LP0_VEC 64 #endif 65 66 /* Environment */ 67 #define CONFIG_ENV_VARS_UBOOT_CONFIG 68 #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ 69 70 /* 71 * Size of malloc() pool 72 */ 73 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ 74 75 /* 76 * PllX Configuration 77 */ 78 #define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */ 79 80 /* 81 * NS16550 Configuration 82 */ 83 #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ 84 85 #define CONFIG_SYS_NS16550 86 #define CONFIG_SYS_NS16550_SERIAL 87 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 88 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 89 90 /* 91 * select serial console configuration 92 */ 93 #define CONFIG_CONS_INDEX 1 94 95 /* allow to overwrite serial and ethaddr */ 96 #define CONFIG_ENV_OVERWRITE 97 #define CONFIG_BAUDRATE 115200 98 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 99 115200} 100 101 /* 102 * This parameter affects a TXFILLTUNING field that controls how much data is 103 * sent to the latency fifo before it is sent to the wire. Without this 104 * parameter, the default (2) causes occasional Data Buffer Errors in OUT 105 * packets depending on the buffer address and size. 106 */ 107 #define CONFIG_USB_EHCI_TXFIFO_THRESH 10 108 #define CONFIG_EHCI_IS_TDI 109 #define CONFIG_EHCI_DCACHE 110 111 /* Total I2C ports on Tegra20 */ 112 #define TEGRA_I2C_NUM_CONTROLLERS 4 113 114 /* include default commands */ 115 #include <config_cmd_default.h> 116 117 /* remove unused commands */ 118 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 119 #undef CONFIG_CMD_FPGA /* FPGA configuration support */ 120 #undef CONFIG_CMD_IMI 121 #undef CONFIG_CMD_IMLS 122 #undef CONFIG_CMD_NFS /* NFS support */ 123 #undef CONFIG_CMD_NET /* network support */ 124 125 /* turn on command-line edit/hist/auto */ 126 #define CONFIG_CMDLINE_EDITING 127 #define CONFIG_COMMAND_HISTORY 128 #define CONFIG_AUTO_COMPLETE 129 130 #define CONFIG_SYS_NO_FLASH 131 132 /* Environment information, boards can override if required */ 133 #define CONFIG_CONSOLE_MUX 134 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 135 #define TEGRA20_DEVICE_SETTINGS "stdin=serial\0" \ 136 "stdout=serial\0" \ 137 "stderr=serial\0" 138 139 #define CONFIG_LOADADDR 0x408000 /* def. location for kernel */ 140 #define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ 141 142 /* 143 * Miscellaneous configurable options 144 */ 145 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 146 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 147 #define CONFIG_SYS_PROMPT V_PROMPT 148 /* 149 * Increasing the size of the IO buffer as default nfsargs size is more 150 * than 256 and so it is not possible to edit it 151 */ 152 #define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */ 153 /* Print Buffer Size */ 154 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 155 sizeof(CONFIG_SYS_PROMPT) + 16) 156 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 157 /* Boot Argument Buffer Size */ 158 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 159 160 #define CONFIG_SYS_MEMTEST_START (TEGRA20_SDRC_CS0 + 0x600000) 161 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) 162 163 #define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */ 164 #define CONFIG_SYS_HZ 1000 165 166 #define CONFIG_STACKBASE 0x2800000 /* 40MB */ 167 168 /*----------------------------------------------------------------------- 169 * Physical Memory Map 170 */ 171 #define CONFIG_NR_DRAM_BANKS 1 172 #define PHYS_SDRAM_1 TEGRA20_SDRC_CS0 173 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ 174 175 #define CONFIG_SYS_TEXT_BASE 0x0010c000 176 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 177 178 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE 179 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN 180 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 181 CONFIG_SYS_INIT_RAM_SIZE - \ 182 GENERATED_GBL_DATA_SIZE) 183 184 #define CONFIG_TEGRA_GPIO 185 #define CONFIG_CMD_GPIO 186 #define CONFIG_CMD_ENTERRCM 187 #define CONFIG_CMD_BOOTZ 188 189 /* Defines for SPL */ 190 #define CONFIG_SPL 191 #define CONFIG_SPL_NAND_SIMPLE 192 #define CONFIG_SPL_TEXT_BASE 0x00108000 193 #define CONFIG_SPL_MAX_SIZE 0x00004000 194 #define CONFIG_SYS_SPL_MALLOC_START 0x00090000 195 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 196 #define CONFIG_SPL_STACK 0x000ffffc 197 198 #define CONFIG_SPL_LIBCOMMON_SUPPORT 199 #define CONFIG_SPL_LIBGENERIC_SUPPORT 200 #define CONFIG_SPL_SERIAL_SUPPORT 201 #define CONFIG_SPL_GPIO_SUPPORT 202 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds" 203 204 #endif /* __TEGRA20_COMMON_H */ 205