1 /*
2  *  (C) Copyright 2010-2012
3  *  NVIDIA Corporation <www.nvidia.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef _TEGRA20_COMMON_H_
9 #define _TEGRA20_COMMON_H_
10 #include "tegra-common.h"
11 
12 /* Cortex-A9 uses a cache line size of 32 bytes */
13 #define CONFIG_SYS_CACHELINE_SIZE	32
14 
15 /*
16  * Errata configuration
17  */
18 #define CONFIG_ARM_ERRATA_716044
19 #define CONFIG_ARM_ERRATA_742230
20 #define CONFIG_ARM_ERRATA_751472
21 
22 /*
23  * NS16550 Configuration
24  */
25 #define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */
26 
27 /*
28  * Miscellaneous configurable options
29  */
30 #define CONFIG_STACKBASE	0x02800000	/* 40MB */
31 
32 /*-----------------------------------------------------------------------
33  * Physical Memory Map
34  */
35 #define CONFIG_SYS_TEXT_BASE	0x00110000
36 
37 /*
38  * Memory layout for where various images get loaded by boot scripts:
39  *
40  * scriptaddr can be pretty much anywhere that doesn't conflict with something
41  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
42  *
43  * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
44  *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
45  *
46  * kernel_addr_r must be within the first 128M of RAM in order for the
47  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
48  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
49  *   should not overlap that area, or the kernel will have to copy itself
50  *   somewhere else before decompression. Similarly, the address of any other
51  *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
52  *   this up to 16M allows for a sizable kernel to be decompressed below the
53  *   compressed load address.
54  *
55  * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
56  *   the compressed kernel to be up to 16M too.
57  *
58  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
59  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
60  */
61 #define CONFIG_LOADADDR 0x01000000
62 #define MEM_LAYOUT_ENV_SETTINGS \
63 	"scriptaddr=0x10000000\0" \
64 	"pxefile_addr_r=0x10100000\0" \
65 	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
66 	"fdt_addr_r=0x02000000\0" \
67 	"ramdisk_addr_r=0x02100000\0"
68 
69 /* Defines for SPL */
70 #define CONFIG_SPL_TEXT_BASE		0x00108000
71 #define CONFIG_SYS_SPL_MALLOC_START	0x00090000
72 #define CONFIG_SPL_STACK		0x000ffffc
73 
74 /* Align LCD to 1MB boundary */
75 #define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE
76 
77 #ifdef CONFIG_TEGRA_LP0
78 #define TEGRA_LP0_ADDR			0x1C406000
79 #define TEGRA_LP0_SIZE			0x2000
80 #define TEGRA_LP0_VEC \
81 	"lp0_vec=" __stringify(TEGRA_LP0_SIZE)  \
82 	"@" __stringify(TEGRA_LP0_ADDR) " "
83 #else
84 #define TEGRA_LP0_VEC
85 #endif
86 
87 /*
88  * This parameter affects a TXFILLTUNING field that controls how much data is
89  * sent to the latency fifo before it is sent to the wire. Without this
90  * parameter, the default (2) causes occasional Data Buffer Errors in OUT
91  * packets depending on the buffer address and size.
92  */
93 #define CONFIG_USB_EHCI_TXFIFO_THRESH	10
94 #define CONFIG_EHCI_IS_TDI
95 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
96 
97 #define CONFIG_SYS_NAND_SELF_INIT
98 #define CONFIG_SYS_NAND_ONFI_DETECTION
99 
100 #endif /* _TEGRA20_COMMON_H_ */
101