1 /* 2 * (C) Copyright 2010-2012 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _TEGRA20_COMMON_H_ 9 #define _TEGRA20_COMMON_H_ 10 #include "tegra-common.h" 11 12 /* 13 * Errata configuration 14 */ 15 #define CONFIG_ARM_ERRATA_716044 16 #define CONFIG_ARM_ERRATA_742230 17 #define CONFIG_ARM_ERRATA_751472 18 19 /* 20 * NS16550 Configuration 21 */ 22 #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ 23 24 /* 25 * Miscellaneous configurable options 26 */ 27 #define CONFIG_STACKBASE 0x02800000 /* 40MB */ 28 29 /*----------------------------------------------------------------------- 30 * Physical Memory Map 31 */ 32 #define CONFIG_SYS_TEXT_BASE 0x00110000 33 34 /* 35 * Memory layout for where various images get loaded by boot scripts: 36 * 37 * scriptaddr can be pretty much anywhere that doesn't conflict with something 38 * else. Put it above BOOTMAPSZ to eliminate conflicts. 39 * 40 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 41 * something else. Put it above BOOTMAPSZ to eliminate conflicts. 42 * 43 * kernel_addr_r must be within the first 128M of RAM in order for the 44 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 45 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 46 * should not overlap that area, or the kernel will have to copy itself 47 * somewhere else before decompression. Similarly, the address of any other 48 * data passed to the kernel shouldn't overlap the start of RAM. Pushing 49 * this up to 16M allows for a sizable kernel to be decompressed below the 50 * compressed load address. 51 * 52 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 53 * the compressed kernel to be up to 16M too. 54 * 55 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 56 * for the FDT/DTB to be up to 1M, which is hopefully plenty. 57 */ 58 #define CONFIG_LOADADDR 0x01000000 59 #define MEM_LAYOUT_ENV_SETTINGS \ 60 "scriptaddr=0x10000000\0" \ 61 "pxefile_addr_r=0x10100000\0" \ 62 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ 63 "fdt_addr_r=0x02000000\0" \ 64 "ramdisk_addr_r=0x02100000\0" 65 66 /* Defines for SPL */ 67 #define CONFIG_SPL_TEXT_BASE 0x00108000 68 #define CONFIG_SYS_SPL_MALLOC_START 0x00090000 69 #define CONFIG_SPL_STACK 0x000ffffc 70 71 /* Align LCD to 1MB boundary */ 72 #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE 73 74 #ifdef CONFIG_TEGRA_LP0 75 #define TEGRA_LP0_ADDR 0x1C406000 76 #define TEGRA_LP0_SIZE 0x2000 77 #define TEGRA_LP0_VEC \ 78 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ 79 "@" __stringify(TEGRA_LP0_ADDR) " " 80 #else 81 #define TEGRA_LP0_VEC 82 #endif 83 84 /* 85 * This parameter affects a TXFILLTUNING field that controls how much data is 86 * sent to the latency fifo before it is sent to the wire. Without this 87 * parameter, the default (2) causes occasional Data Buffer Errors in OUT 88 * packets depending on the buffer address and size. 89 */ 90 #define CONFIG_USB_EHCI_TXFIFO_THRESH 10 91 #define CONFIG_EHCI_IS_TDI 92 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 93 94 #define CONFIG_SYS_NAND_SELF_INIT 95 #define CONFIG_SYS_NAND_ONFI_DETECTION 96 97 #endif /* _TEGRA20_COMMON_H_ */ 98