1 /*
2  *  (C) Copyright 2010-2012
3  *  NVIDIA Corporation <www.nvidia.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef _TEGRA20_COMMON_H_
9 #define _TEGRA20_COMMON_H_
10 #include "tegra-common.h"
11 
12 /*
13  * NS16550 Configuration
14  */
15 #define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */
16 
17 /*
18  * Miscellaneous configurable options
19  */
20 #define CONFIG_STACKBASE	0x02800000	/* 40MB */
21 
22 /*-----------------------------------------------------------------------
23  * Physical Memory Map
24  */
25 
26 /*
27  * Memory layout for where various images get loaded by boot scripts:
28  *
29  * scriptaddr can be pretty much anywhere that doesn't conflict with something
30  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
31  *
32  * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
33  *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
34  *
35  * kernel_addr_r must be within the first 128M of RAM in order for the
36  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
37  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
38  *   should not overlap that area, or the kernel will have to copy itself
39  *   somewhere else before decompression. Similarly, the address of any other
40  *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
41  *   this up to 16M allows for a sizable kernel to be decompressed below the
42  *   compressed load address.
43  *
44  * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
45  *   the compressed kernel to be up to 16M too.
46  *
47  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
48  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
49  */
50 #define CONFIG_LOADADDR 0x01000000
51 #define MEM_LAYOUT_ENV_SETTINGS \
52 	"scriptaddr=0x10000000\0" \
53 	"pxefile_addr_r=0x10100000\0" \
54 	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
55 	"fdt_addr_r=0x02000000\0" \
56 	"ramdisk_addr_r=0x02100000\0"
57 
58 /* Defines for SPL */
59 #define CONFIG_SPL_TEXT_BASE		0x00108000
60 #define CONFIG_SYS_SPL_MALLOC_START	0x00090000
61 #define CONFIG_SPL_STACK		0x000ffffc
62 
63 /* Align LCD to 1MB boundary */
64 #define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE
65 
66 #ifdef CONFIG_TEGRA_LP0
67 #define TEGRA_LP0_ADDR			0x1C406000
68 #define TEGRA_LP0_SIZE			0x2000
69 #define TEGRA_LP0_VEC \
70 	"lp0_vec=" __stringify(TEGRA_LP0_SIZE)  \
71 	"@" __stringify(TEGRA_LP0_ADDR) " "
72 #else
73 #define TEGRA_LP0_VEC
74 #endif
75 
76 /*
77  * This parameter affects a TXFILLTUNING field that controls how much data is
78  * sent to the latency fifo before it is sent to the wire. Without this
79  * parameter, the default (2) causes occasional Data Buffer Errors in OUT
80  * packets depending on the buffer address and size.
81  */
82 #define CONFIG_USB_EHCI_TXFIFO_THRESH	10
83 #define CONFIG_EHCI_IS_TDI
84 
85 #define CONFIG_SYS_NAND_SELF_INIT
86 #define CONFIG_SYS_NAND_ONFI_DETECTION
87 
88 #endif /* _TEGRA20_COMMON_H_ */
89