1 /* 2 * (C) Copyright 2010-2012 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _TEGRA20_COMMON_H_ 9 #define _TEGRA20_COMMON_H_ 10 #include "tegra-common.h" 11 12 /* 13 * Errata configuration 14 */ 15 #define CONFIG_ARM_ERRATA_716044 16 #define CONFIG_ARM_ERRATA_742230 17 #define CONFIG_ARM_ERRATA_751472 18 19 /* 20 * NS16550 Configuration 21 */ 22 #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ 23 24 /* 25 * High Level Configuration Options 26 */ 27 #define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */ 28 29 /* Environment information, boards can override if required */ 30 #define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */ 31 32 /* 33 * Miscellaneous configurable options 34 */ 35 #define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */ 36 #define CONFIG_STACKBASE 0x02800000 /* 40MB */ 37 38 /*----------------------------------------------------------------------- 39 * Physical Memory Map 40 */ 41 #define CONFIG_SYS_TEXT_BASE 0x0010E000 42 43 /* 44 * Memory layout for where various images get loaded by boot scripts: 45 * 46 * scriptaddr can be pretty much anywhere that doesn't conflict with something 47 * else. Put it above BOOTMAPSZ to eliminate conflicts. 48 * 49 * kernel_addr_r must be within the first 128M of RAM in order for the 50 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 51 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 52 * should not overlap that area, or the kernel will have to copy itself 53 * somewhere else before decompression. Similarly, the address of any other 54 * data passed to the kernel shouldn't overlap the start of RAM. Pushing 55 * this up to 16M allows for a sizable kernel to be decompressed below the 56 * compressed load address. 57 * 58 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 59 * the compressed kernel to be up to 16M too. 60 * 61 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 62 * for the FDT/DTB to be up to 1M, which is hopefully plenty. 63 */ 64 #define MEM_LAYOUT_ENV_SETTINGS \ 65 "scriptaddr=0x10000000\0" \ 66 "kernel_addr_r=0x01000000\0" \ 67 "fdt_addr_r=0x02000000\0" \ 68 "ramdisk_addr_r=0x02100000\0" 69 70 /* Defines for SPL */ 71 #define CONFIG_SPL_TEXT_BASE 0x00108000 72 #define CONFIG_SYS_SPL_MALLOC_START 0x00090000 73 #define CONFIG_SPL_STACK 0x000ffffc 74 75 /* Align LCD to 1MB boundary */ 76 #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE 77 78 #ifdef CONFIG_TEGRA_LP0 79 #define TEGRA_LP0_ADDR 0x1C406000 80 #define TEGRA_LP0_SIZE 0x2000 81 #define TEGRA_LP0_VEC \ 82 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ 83 "@" __stringify(TEGRA_LP0_ADDR) " " 84 #else 85 #define TEGRA_LP0_VEC 86 #endif 87 88 /* 89 * This parameter affects a TXFILLTUNING field that controls how much data is 90 * sent to the latency fifo before it is sent to the wire. Without this 91 * parameter, the default (2) causes occasional Data Buffer Errors in OUT 92 * packets depending on the buffer address and size. 93 */ 94 #define CONFIG_USB_EHCI_TXFIFO_THRESH 10 95 #define CONFIG_EHCI_IS_TDI 96 97 /* Total I2C ports on Tegra20 */ 98 #define TEGRA_I2C_NUM_CONTROLLERS 4 99 100 #define CONFIG_SYS_NAND_SELF_INIT 101 #define CONFIG_SYS_NAND_ONFI_DETECTION 102 103 #endif /* _TEGRA20_COMMON_H_ */ 104