1 /*
2  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * SPDX-License-Identifier:	GPL-2.0
5  */
6 
7 #ifndef _TEGRA114_COMMON_H_
8 #define _TEGRA114_COMMON_H_
9 #include "tegra-common.h"
10 
11 /*
12  * NS16550 Configuration
13  */
14 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
15 
16 /*
17  * Miscellaneous configurable options
18  */
19 #define CONFIG_STACKBASE	0x82800000	/* 40MB */
20 
21 /*-----------------------------------------------------------------------
22  * Physical Memory Map
23  */
24 
25 /*
26  * Memory layout for where various images get loaded by boot scripts:
27  *
28  * scriptaddr can be pretty much anywhere that doesn't conflict with something
29  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
30  *
31  * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
32  *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
33  *
34  * kernel_addr_r must be within the first 128M of RAM in order for the
35  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
36  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
37  *   should not overlap that area, or the kernel will have to copy itself
38  *   somewhere else before decompression. Similarly, the address of any other
39  *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
40  *   this up to 16M allows for a sizable kernel to be decompressed below the
41  *   compressed load address.
42  *
43  * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
44  *   the compressed kernel to be up to 16M too.
45  *
46  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
47  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
48  */
49 #define CONFIG_LOADADDR 0x81000000
50 #define MEM_LAYOUT_ENV_SETTINGS \
51 	"scriptaddr=0x90000000\0" \
52 	"pxefile_addr_r=0x90100000\0" \
53 	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
54 	"fdt_addr_r=0x82000000\0" \
55 	"ramdisk_addr_r=0x82100000\0"
56 
57 /* Defines for SPL */
58 #define CONFIG_SPL_TEXT_BASE		0x80108000
59 #define CONFIG_SYS_SPL_MALLOC_START	0x80090000
60 #define CONFIG_SPL_STACK		0x800ffffc
61 
62 /* For USB EHCI controller */
63 #define CONFIG_EHCI_IS_TDI
64 #define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
65 
66 #endif /* _TEGRA114_COMMON_H_ */
67