xref: /openbmc/u-boot/include/configs/tbs2910.h (revision 8cb78722)
1 /*
2  * Copyright (C) 2014 Soeren Moch <smoch@web.de>
3  *
4  * Configuration settings for the TBS2910 MatrixARM board.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __TBS2910_CONFIG_H
10 #define __TBS2910_CONFIG_H
11 
12 #include "mx6_common.h"
13 #include <asm/arch/imx-regs.h>
14 #include <asm/imx-common/gpio.h>
15 
16 /* General configuration */
17 #define CONFIG_MX6
18 #define CONFIG_DISPLAY_CPUINFO
19 #define CONFIG_DISPLAY_BOARDINFO_LATE
20 #define CONFIG_SYS_THUMB_BUILD
21 
22 #define CONFIG_MACH_TYPE		3980
23 
24 #define CONFIG_CMDLINE_TAG
25 #define CONFIG_SETUP_MEMORY_TAGS
26 #define CONFIG_INITRD_TAG
27 #define CONFIG_REVISION_TAG
28 #define CONFIG_SYS_GENERIC_BOARD
29 
30 #define CONFIG_BOARD_EARLY_INIT_F
31 #define CONFIG_MXC_GPIO
32 #define CONFIG_CMD_GPIO
33 
34 #define CONFIG_SYS_LONGHELP
35 #define CONFIG_SYS_HUSH_PARSER
36 #define CONFIG_SYS_PROMPT		"Matrix U-Boot> "
37 #define CONFIG_BOOTDELAY		3
38 #define CONFIG_AUTO_COMPLETE
39 #define CONFIG_CMDLINE_EDITING
40 #define CONFIG_SYS_MAXARGS		16
41 #define CONFIG_SYS_CBSIZE		1024
42 #define CONFIG_SYS_PBSIZE \
43 	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
44 #define CONFIG_SYS_HZ			1000
45 
46 /* Physical Memory Map */
47 #define CONFIG_NR_DRAM_BANKS		1
48 #define CONFIG_SYS_SDRAM_BASE		MMDC0_ARB_BASE_ADDR
49 
50 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
51 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
52 #define CONFIG_SYS_INIT_SP_OFFSET \
53 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
54 #define CONFIG_SYS_INIT_SP_ADDR \
55 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
56 
57 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024 * 1024)
58 
59 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
60 #define CONFIG_SYS_MEMTEST_END \
61 	(CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
62 
63 #define CONFIG_SYS_TEXT_BASE		0x80000000
64 #define CONFIG_SYS_BOOTMAPSZ		0x6C000000
65 #define CONFIG_SYS_LOAD_ADDR		0x10800000
66 
67 /* Serial console */
68 #define CONFIG_MXC_UART
69 #define CONFIG_MXC_UART_BASE		UART1_BASE /* select UART1/UART2 */
70 #define CONFIG_BAUDRATE			115200
71 
72 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
73 #define CONFIG_CONSOLE_MUX
74 #define CONFIG_CONS_INDEX		1
75 
76 /* *** Command definition *** */
77 #include <config_cmd_default.h>
78 
79 #undef CONFIG_CMD_IMLS
80 
81 #define CONFIG_CMD_BMODE
82 #define CONFIG_CMD_SETEXPR
83 #define CONFIG_CMD_MEMTEST
84 #define CONFIG_CMD_TIME
85 
86 /* Filesystems / image support */
87 #define CONFIG_CMD_EXT4
88 #define CONFIG_CMD_FAT
89 #define CONFIG_DOS_PARTITION
90 #define CONFIG_EFI_PARTITION
91 #define CONFIG_CMD_FS_GENERIC
92 
93 #define CONFIG_OF_LIBFDT
94 #define CONFIG_CMD_BOOTZ
95 #define CONFIG_SUPPORT_RAW_INITRD
96 #define CONFIG_FIT
97 
98 /* MMC */
99 #define CONFIG_FSL_ESDHC
100 #define CONFIG_FSL_USDHC
101 #define CONFIG_SYS_FSL_USDHC_NUM	3
102 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
103 
104 #define CONFIG_MMC
105 #define CONFIG_CMD_MMC
106 #define CONFIG_GENERIC_MMC
107 #define CONFIG_BOUNCE_BUFFER
108 
109 /* Ethernet */
110 #define CONFIG_FEC_MXC
111 #define CONFIG_CMD_PING
112 #define CONFIG_CMD_DHCP
113 #define CONFIG_CMD_MII
114 #define CONFIG_CMD_NET
115 #define CONFIG_FEC_MXC
116 #define CONFIG_MII
117 #define IMX_FEC_BASE			ENET_BASE_ADDR
118 #define CONFIG_FEC_XCV_TYPE		RGMII
119 #define CONFIG_ETHPRIME			"FEC"
120 #define CONFIG_FEC_MXC_PHYADDR		4
121 #define CONFIG_PHYLIB
122 #define CONFIG_PHY_ATHEROS
123 
124 /* Framebuffer */
125 #define CONFIG_VIDEO
126 #ifdef CONFIG_VIDEO
127 #define CONFIG_VIDEO_IPUV3
128 #define CONFIG_IPUV3_CLK		260000000
129 #define CONFIG_CFB_CONSOLE
130 #define CONFIG_CFB_CONSOLE_ANSI
131 #define CONFIG_VIDEO_SW_CURSOR
132 #define CONFIG_VGA_AS_SINGLE_DEVICE
133 #define CONFIG_VIDEO_BMP_RLE8
134 #define CONFIG_IMX_HDMI
135 #define CONFIG_IMX_VIDEO_SKIP
136 #define CONFIG_CMD_HDMIDETECT
137 #endif
138 
139 /* PCI */
140 #define CONFIG_CMD_PCI
141 #ifdef CONFIG_CMD_PCI
142 #define CONFIG_PCI
143 #define CONFIG_PCI_PNP
144 #define CONFIG_PCI_SCAN_SHOW
145 #define CONFIG_PCIE_IMX
146 #define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
147 #endif
148 
149 /* SATA */
150 #define CONFIG_CMD_SATA
151 #ifdef CONFIG_CMD_SATA
152 #define CONFIG_DWC_AHSATA
153 #define CONFIG_SYS_SATA_MAX_DEVICE	1
154 #define CONFIG_DWC_AHSATA_PORT_ID	0
155 #define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
156 #define CONFIG_LBA48
157 #define CONFIG_LIBATA
158 #endif
159 
160 /* USB */
161 #define CONFIG_CMD_USB
162 #ifdef CONFIG_CMD_USB
163 #define CONFIG_USB_EHCI
164 #define CONFIG_USB_EHCI_MX6
165 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
166 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
167 #define CONFIG_USB_STORAGE
168 #define CONFIG_CMD_USB_MASS_STORAGE
169 #ifdef CONFIG_CMD_USB_MASS_STORAGE
170 #define CONFIG_CI_UDC
171 #define CONFIG_USBD_HS
172 #define CONFIG_USB_GADGET
173 #define CONFIG_USB_GADGET_MASS_STORAGE
174 #define CONFIG_USB_GADGET_DUALSPEED
175 #define CONFIG_USB_GADGET_VBUS_DRAW	0
176 #define CONFIG_USBDOWNLOAD_GADGET
177 #define CONFIG_G_DNL_VENDOR_NUM		0x0525
178 #define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
179 #define CONFIG_G_DNL_MANUFACTURER	"TBS"
180 #endif /* CONFIG_CMD_USB_MASS_STORAGE */
181 #define CONFIG_USB_KEYBOARD
182 #ifdef CONFIG_USB_KEYBOARD
183 #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
184 #define CONFIG_SYS_STDIO_DEREGISTER
185 #define CONFIG_PREBOOT "if hdmidet; then usb start; fi"
186 #endif /* CONFIG_USB_KEYBOARD */
187 #endif /* CONFIG_CMD_USB      */
188 
189 /* RTC */
190 #define CONFIG_CMD_DATE
191 #ifdef CONFIG_CMD_DATE
192 #define CONFIG_CMD_I2C
193 #define CONFIG_RTC_DS1307
194 #define CONFIG_SYS_RTC_BUS_NUM		2
195 #endif
196 
197 /* I2C */
198 #define CONFIG_CMD_I2C
199 #ifdef CONFIG_CMD_I2C
200 #define CONFIG_SYS_I2C
201 #define CONFIG_SYS_I2C_MXC
202 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
203 #define CONFIG_SYS_I2C_SPEED		100000
204 #define CONFIG_I2C_EDID
205 #endif
206 
207 /* Fuses */
208 #define CONFIG_CMD_FUSE
209 #ifdef CONFIG_CMD_FUSE
210 #define CONFIG_MXC_OCOTP
211 #endif
212 
213 #ifndef CONFIG_SYS_DCACHE_OFF
214 #define CONFIG_CMD_CACHE
215 #endif
216 
217 /* Flash and environment organization */
218 #define CONFIG_SYS_NO_FLASH
219 
220 #define CONFIG_ENV_IS_IN_MMC
221 #define CONFIG_SYS_MMC_ENV_DEV		2
222 #define CONFIG_SYS_MMC_ENV_PART		1
223 #define CONFIG_ENV_SIZE			(8 * 1024)
224 #define CONFIG_ENV_OFFSET		(384 * 1024)
225 #define CONFIG_ENV_OVERWRITE
226 
227 #define CONFIG_EXTRA_ENV_SETTINGS \
228 	"bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
229 	"bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
230 			"video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
231 	"bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \
232 	"bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \
233 			"${bootargs_mmc3}\0" \
234 	"bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
235 			"rdinit=/sbin/init enable_wait_mode=off\0" \
236 	"bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
237 			"mmc read 0x10800000 0x800 0x4000; bootm\0" \
238 	"bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
239 	"bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
240 			"run bootargs_upd; " \
241 			"bootm 0x10800000 0x10d00000\0" \
242 	"console=ttymxc0\0" \
243 	"fan=gpio set 92\0" \
244 	"stdin=serial,usbkbd\0" \
245 	"stdout=serial,vga\0" \
246 	"stderr=serial,vga\0"
247 
248 #define CONFIG_BOOTCOMMAND \
249 	"mmc rescan; " \
250 	"if run bootcmd_up1; then " \
251 		"run bootcmd_up2; " \
252 	"else " \
253 		"run bootcmd_mmc; " \
254 	"fi"
255 
256 #endif			       /* __TBS2910_CONFIG_H * */
257