xref: /openbmc/u-boot/include/configs/taurus.h (revision 8ee59472)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Common board functions for Siemens TAURUS (AT91SAM9G20) based boards
4  * (C) Copyright 2013 Siemens AG
5  *
6  * Based on:
7  * U-Boot file: include/configs/at91sam9260ek.h
8  *
9  * (C) Copyright 2007-2008
10  * Stelian Pop <stelian@popies.net>
11  * Lead Tech Design <www.leadtechdesign.com>
12  */
13 
14 #ifndef __CONFIG_H
15 #define __CONFIG_H
16 
17 /*
18  * SoC must be defined first, before hardware.h is included.
19  * In this case SoC is defined in boards.cfg.
20  */
21 #include <asm/hardware.h>
22 #include <linux/sizes.h>
23 
24 #if defined(CONFIG_SPL_BUILD)
25 #define CONFIG_SYS_ICACHE_OFF
26 #define CONFIG_SYS_DCACHE_OFF
27 #endif
28 /*
29  * Warning: changing CONFIG_SYS_TEXT_BASE requires
30  * adapting the initial boot program.
31  * Since the linker has to swallow that define, we must use a pure
32  * hex number here!
33  */
34 
35 /* ARM asynchronous clock */
36 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
37 #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
38 
39 /* Misc CPU related */
40 #define CONFIG_ARCH_CPU_INIT
41 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
42 #define CONFIG_SETUP_MEMORY_TAGS
43 #define CONFIG_INITRD_TAG
44 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
45 
46 /* general purpose I/O */
47 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
48 #define CONFIG_AT91_GPIO
49 #define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
50 
51 /* serial console */
52 #define CONFIG_ATMEL_USART
53 #define CONFIG_USART_BASE		ATMEL_BASE_DBGU
54 #define CONFIG_USART_ID			ATMEL_ID_SYS
55 
56 
57 /*
58  * SDRAM: 1 bank, min 32, max 128 MB
59  * Initialized before u-boot gets started.
60  */
61 #define CONFIG_NR_DRAM_BANKS		1
62 #define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
63 #define CONFIG_SYS_SDRAM_SIZE		(128 * SZ_1M)
64 
65 /*
66  * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
67  * leaving the correct space for initial global data structure above
68  * that address while providing maximum stack area below.
69  */
70 #define CONFIG_SYS_INIT_SP_ADDR \
71 	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
72 
73 /* NAND flash */
74 #ifdef CONFIG_CMD_NAND
75 #define CONFIG_NAND_ATMEL
76 #define CONFIG_SYS_MAX_NAND_DEVICE	1
77 #define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
78 #define CONFIG_SYS_NAND_DBW_8
79 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
80 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
81 #define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
82 #define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
83 #endif
84 
85 /* Ethernet */
86 #define CONFIG_MACB
87 #define CONFIG_RMII
88 #define CONFIG_AT91_WANTS_COMMON_PHY
89 
90 #define CONFIG_AT91SAM9_WATCHDOG
91 #define CONFIG_AT91_HW_WDT_TIMEOUT	15
92 #if !defined(CONFIG_SPL_BUILD)
93 /* Enable the watchdog */
94 #define CONFIG_HW_WATCHDOG
95 #endif
96 
97 /* USB */
98 #if defined(CONFIG_BOARD_TAURUS)
99 #define CONFIG_USB_ATMEL
100 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
101 #define CONFIG_USB_OHCI_NEW
102 #define CONFIG_SYS_USB_OHCI_CPU_INIT
103 #define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000
104 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
105 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
106 
107 /* USB DFU support */
108 #define CONFIG_MTD_DEVICE
109 #define CONFIG_MTD_PARTITIONS
110 
111 #define CONFIG_USB_GADGET_AT91
112 
113 /* DFU class support */
114 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
115 #define DFU_MANIFEST_POLL_TIMEOUT	25000
116 #endif
117 
118 /* SPI EEPROM */
119 #define TAURUS_SPI_MASK (1 << 4)
120 #define TAURUS_SPI_CS_PIN	AT91_PIN_PA3
121 
122 #if defined(CONFIG_SPL_BUILD)
123 /* SPL related */
124 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
125 
126 #define CONFIG_SF_DEFAULT_BUS 0
127 #define CONFIG_SF_DEFAULT_SPEED 1000000
128 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
129 #endif
130 
131 /* load address */
132 #define CONFIG_SYS_LOAD_ADDR			0x22000000
133 
134 /* bootstrap in spi flash , u-boot + env + linux in nandflash */
135 #define CONFIG_ENV_OFFSET		0x100000
136 #define CONFIG_ENV_OFFSET_REDUND	0x180000
137 #define CONFIG_ENV_SIZE		(SZ_128K)	/* 1 sector = 128 kB */
138 #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
139 
140 /*
141  * Size of malloc() pool
142  */
143 #define CONFIG_SYS_MALLOC_LEN \
144 	ROUND(3 * CONFIG_ENV_SIZE + SZ_4M, 0x1000)
145 
146 /* Defines for SPL */
147 #define CONFIG_SPL_TEXT_BASE		0x0
148 #define CONFIG_SPL_MAX_SIZE		(31 * SZ_512)
149 #define	CONFIG_SPL_STACK		(ATMEL_BASE_SRAM1 + SZ_16K)
150 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
151 					CONFIG_SYS_MALLOC_LEN)
152 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
153 
154 #define CONFIG_SPL_BSS_START_ADDR	CONFIG_SPL_MAX_SIZE
155 #define CONFIG_SPL_BSS_MAX_SIZE		(3 * SZ_512)
156 
157 #define CONFIG_SYS_NAND_ENABLE_PIN_SPL	(2*32 + 14)
158 #define CONFIG_SYS_USE_NANDFLASH	1
159 #define CONFIG_SPL_NAND_DRIVERS
160 #define CONFIG_SPL_NAND_BASE
161 #define CONFIG_SPL_NAND_ECC
162 #define CONFIG_SPL_NAND_RAW_ONLY
163 #define CONFIG_SPL_NAND_SOFTECC
164 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x20000
165 #define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
166 #define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
167 #define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
168 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
169 
170 #define CONFIG_SYS_NAND_SIZE		(256 * SZ_1M)
171 #define CONFIG_SYS_NAND_PAGE_SIZE	SZ_2K
172 #define CONFIG_SYS_NAND_BLOCK_SIZE	(SZ_128K)
173 #define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
174 					 CONFIG_SYS_NAND_PAGE_SIZE)
175 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
176 #define CONFIG_SYS_NAND_ECCSIZE		256
177 #define CONFIG_SYS_NAND_ECCBYTES	3
178 #define CONFIG_SYS_NAND_OOBSIZE		64
179 #define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
180 					  48, 49, 50, 51, 52, 53, 54, 55, \
181 					  56, 57, 58, 59, 60, 61, 62, 63, }
182 
183 #define CONFIG_SPL_ATMEL_SIZE
184 #define CONFIG_SYS_MASTER_CLOCK		132096000
185 #define AT91_PLL_LOCK_TIMEOUT		1000000
186 #define CONFIG_SYS_AT91_PLLA		0x202A3F01
187 #define CONFIG_SYS_MCKR			0x1300
188 #define CONFIG_SYS_MCKR_CSS		(0x02 | CONFIG_SYS_MCKR)
189 #define CONFIG_SYS_AT91_PLLB		0x10193F05
190 
191 #endif
192