1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP /* in a TI OMAP core */ 20 21 #define CONFIG_OMAP_GPIO 22 23 #define CONFIG_SDRC /* Has an SDRC controller */ 24 25 #include <asm/arch/cpu.h> /* get chip and board defs */ 26 #include <asm/arch/omap.h> 27 28 /* Clock Defines */ 29 #define V_OSCK 26000000 /* Clock output from T2 */ 30 #define V_SCLK (V_OSCK >> 1) 31 32 #define CONFIG_MISC_INIT_R 33 34 #define CONFIG_CMDLINE_TAG 35 #define CONFIG_SETUP_MEMORY_TAGS 36 #define CONFIG_INITRD_TAG 37 #define CONFIG_REVISION_TAG 38 39 /* 40 * Size of malloc() pool 41 */ 42 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 43 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 44 45 /* 46 * Hardware drivers 47 */ 48 49 /* 50 * NS16550 Configuration 51 */ 52 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 53 54 #define CONFIG_SYS_NS16550_SERIAL 55 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 56 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 57 58 /* 59 * select serial console configuration 60 */ 61 #define CONFIG_CONS_INDEX 3 62 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 63 64 /* allow to overwrite serial and ethaddr */ 65 #define CONFIG_ENV_OVERWRITE 66 67 /* GPIO banks */ 68 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ 69 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ 70 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ 71 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ 72 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ 73 74 /* commands to include */ 75 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 76 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 77 #define MTDIDS_DEFAULT "nand0=nand" 78 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 79 "1920k(u-boot),128k(u-boot-env),"\ 80 "4m(kernel),-(fs)" 81 82 #define CONFIG_CMD_NAND /* NAND support */ 83 84 #define CONFIG_SYS_I2C 85 #define CONFIG_SYS_I2C_OMAP34XX 86 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 87 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 88 #define CONFIG_I2C_MULTI_BUS 89 90 /* 91 * TWL4030 92 */ 93 #define CONFIG_TWL4030_POWER 94 #define CONFIG_TWL4030_LED 95 96 /* 97 * Board NAND Info. 98 */ 99 #define CONFIG_NAND_OMAP_GPMC 100 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 101 /* to access nand */ 102 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 103 /* to access nand at */ 104 /* CS0 */ 105 106 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 107 /* devices */ 108 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 109 /* Environment information */ 110 111 #define CONFIG_EXTRA_ENV_SETTINGS \ 112 "loadaddr=0x82000000\0" \ 113 "console=ttyO2,115200n8\0" \ 114 "mpurate=600\0" \ 115 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 116 "tv_mode=omapfb.mode=tv:ntsc\0" \ 117 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 118 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 119 "extra_options= \0" \ 120 "mmcdev=0\0" \ 121 "mmcroot=/dev/mmcblk0p2 rw\0" \ 122 "mmcrootfstype=ext3 rootwait\0" \ 123 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 124 "nandrootfstype=ubifs\0" \ 125 "mmcargs=setenv bootargs console=${console} " \ 126 "mpurate=${mpurate} " \ 127 "${video_mode} " \ 128 "root=${mmcroot} " \ 129 "rootfstype=${mmcrootfstype} " \ 130 "${extra_options}\0" \ 131 "nandargs=setenv bootargs console=${console} " \ 132 "mpurate=${mpurate} " \ 133 "${video_mode} " \ 134 "${network_setting} " \ 135 "root=${nandroot} " \ 136 "rootfstype=${nandrootfstype} "\ 137 "${extra_options}\0" \ 138 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 139 "bootscript=echo Running bootscript from mmc ...; " \ 140 "source ${loadaddr}\0" \ 141 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 142 "mmcboot=echo Booting from mmc ...; " \ 143 "run mmcargs; " \ 144 "bootm ${loadaddr}\0" \ 145 "nandboot=echo Booting from nand ...; " \ 146 "run nandargs; " \ 147 "nand read ${loadaddr} 280000 400000; " \ 148 "bootm ${loadaddr}\0" \ 149 150 #define CONFIG_BOOTCOMMAND \ 151 "if mmc rescan ${mmcdev}; then " \ 152 "if run loadbootscript; then " \ 153 "run bootscript; " \ 154 "else " \ 155 "if run loaduimage; then " \ 156 "run mmcboot; " \ 157 "else run nandboot; " \ 158 "fi; " \ 159 "fi; " \ 160 "else run nandboot; fi" 161 162 /* 163 * Miscellaneous configurable options 164 */ 165 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 166 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 167 168 /* turn on command-line edit/hist/auto */ 169 #define CONFIG_CMDLINE_EDITING 170 #define CONFIG_COMMAND_HISTORY 171 #define CONFIG_AUTO_COMPLETE 172 173 /* Print Buffer Size */ 174 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 175 sizeof(CONFIG_SYS_PROMPT) + 16) 176 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 177 /* Boot Argument Buffer Size */ 178 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 179 180 #define CONFIG_SYS_ALT_MEMTEST 1 181 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 182 /* defaults */ 183 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 184 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 185 186 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 187 /* load address */ 188 #define CONFIG_SYS_TEXT_BASE 0x80008000 189 190 /* 191 * OMAP3 has 12 GP timers, they can be driven by the system clock 192 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 193 * This rate is divided by a local divisor. 194 */ 195 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 196 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 197 198 /* 199 * Physical Memory Map 200 */ 201 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 202 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 203 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 204 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 205 206 /* 207 * FLASH and environment organization 208 */ 209 210 /* **** PISMO SUPPORT *** */ 211 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 212 #define CONFIG_SYS_FLASH_BASE NAND_BASE 213 214 /* Monitor at start of flash */ 215 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 216 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 217 218 #define CONFIG_ENV_IS_IN_NAND 1 219 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 220 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 221 222 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 223 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 224 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 225 226 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 227 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 228 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 229 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 230 CONFIG_SYS_INIT_RAM_SIZE - \ 231 GENERATED_GBL_DATA_SIZE) 232 233 #define CONFIG_OMAP3_SPI 234 235 /* 236 * USB 237 * 238 * Currently only EHCI is enabled, the MUSB OTG controller 239 * is not enabled. 240 */ 241 242 /* USB EHCI */ 243 #define CONFIG_USB_EHCI 244 #define CONFIG_USB_EHCI_OMAP 245 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 246 247 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 248 #define CONFIG_USB_HOST_ETHER 249 #define CONFIG_USB_ETHER_SMSC95XX 250 251 #define CONFIG_USB_ETHER 252 #define CONFIG_USB_ETHER_RNDIS 253 254 /* Defines for SPL */ 255 #define CONFIG_SPL_FRAMEWORK 256 #define CONFIG_SPL_NAND_SIMPLE 257 258 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 259 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 260 261 #define CONFIG_SPL_BOARD_INIT 262 #define CONFIG_SPL_NAND_BASE 263 #define CONFIG_SPL_NAND_DRIVERS 264 #define CONFIG_SPL_NAND_ECC 265 #define CONFIG_SPL_OMAP3_ID_NAND 266 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 267 268 /* NAND boot config */ 269 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 270 #define CONFIG_SYS_NAND_PAGE_COUNT 64 271 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 272 #define CONFIG_SYS_NAND_OOBSIZE 64 273 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 274 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 275 /* 276 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 277 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 278 */ 279 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 280 10, 11, 12, 13 } 281 #define CONFIG_SYS_NAND_ECCSIZE 512 282 #define CONFIG_SYS_NAND_ECCBYTES 3 283 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 284 285 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 286 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 287 288 #define CONFIG_SPL_TEXT_BASE 0x40200800 289 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 290 CONFIG_SPL_TEXT_BASE) 291 292 /* 293 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 294 * older x-loader implementations. And move the BSS area so that it 295 * doesn't overlap with TEXT_BASE. 296 */ 297 #define CONFIG_SYS_TEXT_BASE 0x80008000 298 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 299 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 300 301 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 302 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 303 304 #endif /* __CONFIG_H */ 305