1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuration settings for the TechNexion TAO-3530 SOM 4 * equipped on Thunder baseboard. 5 * 6 * Edward Lin <linuxfae@technexion.com> 7 * Tapani Utriainen <linuxfae@technexion.com> 8 * 9 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 19 #include <asm/arch/cpu.h> /* get chip and board defs */ 20 #include <asm/arch/omap.h> 21 22 /* Clock Defines */ 23 #define V_OSCK 26000000 /* Clock output from T2 */ 24 #define V_SCLK (V_OSCK >> 1) 25 26 #define CONFIG_CMDLINE_TAG 27 #define CONFIG_SETUP_MEMORY_TAGS 28 #define CONFIG_INITRD_TAG 29 #define CONFIG_REVISION_TAG 30 31 /* 32 * Size of malloc() pool 33 */ 34 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 35 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 36 37 /* 38 * Hardware drivers 39 */ 40 41 /* 42 * NS16550 Configuration 43 */ 44 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 45 46 #define CONFIG_SYS_NS16550_SERIAL 47 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 48 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 49 50 /* 51 * select serial console configuration 52 */ 53 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 54 55 /* allow to overwrite serial and ethaddr */ 56 #define CONFIG_ENV_OVERWRITE 57 58 /* commands to include */ 59 60 #define CONFIG_SYS_I2C 61 #define CONFIG_I2C_MULTI_BUS 62 63 /* 64 * TWL4030 65 */ 66 67 /* 68 * Board NAND Info. 69 */ 70 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 71 /* to access nand at */ 72 /* CS0 */ 73 74 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 75 /* devices */ 76 /* Environment information */ 77 78 #define CONFIG_EXTRA_ENV_SETTINGS \ 79 "loadaddr=0x82000000\0" \ 80 "console=ttyO2,115200n8\0" \ 81 "mpurate=600\0" \ 82 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 83 "tv_mode=omapfb.mode=tv:ntsc\0" \ 84 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 85 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 86 "extra_options= \0" \ 87 "mmcdev=0\0" \ 88 "mmcroot=/dev/mmcblk0p2 rw\0" \ 89 "mmcrootfstype=ext3 rootwait\0" \ 90 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 91 "nandrootfstype=ubifs\0" \ 92 "mmcargs=setenv bootargs console=${console} " \ 93 "mpurate=${mpurate} " \ 94 "${video_mode} " \ 95 "root=${mmcroot} " \ 96 "rootfstype=${mmcrootfstype} " \ 97 "${extra_options}\0" \ 98 "nandargs=setenv bootargs console=${console} " \ 99 "mpurate=${mpurate} " \ 100 "${video_mode} " \ 101 "${network_setting} " \ 102 "root=${nandroot} " \ 103 "rootfstype=${nandrootfstype} "\ 104 "${extra_options}\0" \ 105 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 106 "bootscript=echo Running bootscript from mmc ...; " \ 107 "source ${loadaddr}\0" \ 108 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 109 "mmcboot=echo Booting from mmc ...; " \ 110 "run mmcargs; " \ 111 "bootm ${loadaddr}\0" \ 112 "nandboot=echo Booting from nand ...; " \ 113 "run nandargs; " \ 114 "nand read ${loadaddr} 280000 400000; " \ 115 "bootm ${loadaddr}\0" \ 116 117 #define CONFIG_BOOTCOMMAND \ 118 "if mmc rescan ${mmcdev}; then " \ 119 "if run loadbootscript; then " \ 120 "run bootscript; " \ 121 "else " \ 122 "if run loaduimage; then " \ 123 "run mmcboot; " \ 124 "else run nandboot; " \ 125 "fi; " \ 126 "fi; " \ 127 "else run nandboot; fi" 128 129 /* 130 * Miscellaneous configurable options 131 */ 132 133 /* turn on command-line edit/hist/auto */ 134 135 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 136 /* defaults */ 137 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 138 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 139 140 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 141 /* load address */ 142 143 /* 144 * OMAP3 has 12 GP timers, they can be driven by the system clock 145 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 146 * This rate is divided by a local divisor. 147 */ 148 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 149 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 150 151 /* 152 * Physical Memory Map 153 */ 154 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 155 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 156 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 157 158 /* 159 * FLASH and environment organization 160 */ 161 162 /* **** PISMO SUPPORT *** */ 163 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 164 #define CONFIG_SYS_FLASH_BASE NAND_BASE 165 166 /* Monitor at start of flash */ 167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 168 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 169 170 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 171 172 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 173 #define CONFIG_ENV_OFFSET 0x260000 174 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 175 176 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 177 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 178 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 179 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 180 CONFIG_SYS_INIT_RAM_SIZE - \ 181 GENERATED_GBL_DATA_SIZE) 182 183 /* 184 * USB 185 * 186 * Currently only EHCI is enabled, the MUSB OTG controller 187 * is not enabled. 188 */ 189 190 /* USB EHCI */ 191 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 192 193 /* Defines for SPL */ 194 195 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 196 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 197 198 #define CONFIG_SPL_NAND_BASE 199 #define CONFIG_SPL_NAND_DRIVERS 200 #define CONFIG_SPL_NAND_ECC 201 202 /* NAND boot config */ 203 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 204 #define CONFIG_SYS_NAND_PAGE_COUNT 64 205 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 206 #define CONFIG_SYS_NAND_OOBSIZE 64 207 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 208 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 209 /* 210 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 211 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 212 */ 213 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 214 10, 11, 12, 13 } 215 #define CONFIG_SYS_NAND_ECCSIZE 512 216 #define CONFIG_SYS_NAND_ECCBYTES 3 217 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 218 219 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 220 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 221 222 #define CONFIG_SPL_TEXT_BASE 0x40200800 223 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 224 CONFIG_SPL_TEXT_BASE) 225 226 /* 227 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 228 * older x-loader implementations. And move the BSS area so that it 229 * doesn't overlap with TEXT_BASE. 230 */ 231 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 232 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 233 234 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 235 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 236 237 #endif /* __CONFIG_H */ 238