1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 20 #include <asm/arch/cpu.h> /* get chip and board defs */ 21 #include <asm/arch/omap.h> 22 23 /* Clock Defines */ 24 #define V_OSCK 26000000 /* Clock output from T2 */ 25 #define V_SCLK (V_OSCK >> 1) 26 27 #define CONFIG_MISC_INIT_R 28 29 #define CONFIG_CMDLINE_TAG 30 #define CONFIG_SETUP_MEMORY_TAGS 31 #define CONFIG_INITRD_TAG 32 #define CONFIG_REVISION_TAG 33 34 /* 35 * Size of malloc() pool 36 */ 37 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 38 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 39 40 /* 41 * Hardware drivers 42 */ 43 44 /* 45 * NS16550 Configuration 46 */ 47 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 48 49 #define CONFIG_SYS_NS16550_SERIAL 50 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 51 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 52 53 /* 54 * select serial console configuration 55 */ 56 #define CONFIG_CONS_INDEX 3 57 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 58 59 /* allow to overwrite serial and ethaddr */ 60 #define CONFIG_ENV_OVERWRITE 61 62 /* commands to include */ 63 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 64 #define MTDIDS_DEFAULT "nand0=nand" 65 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 66 "1920k(u-boot),128k(u-boot-env),"\ 67 "4m(kernel),-(fs)" 68 69 #define CONFIG_SYS_I2C 70 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 71 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 72 #define CONFIG_I2C_MULTI_BUS 73 74 /* 75 * TWL4030 76 */ 77 #define CONFIG_TWL4030_LED 78 79 /* 80 * Board NAND Info. 81 */ 82 #define CONFIG_NAND_OMAP_GPMC 83 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 84 /* to access nand */ 85 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 86 /* to access nand at */ 87 /* CS0 */ 88 89 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 90 /* devices */ 91 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 92 /* Environment information */ 93 94 #define CONFIG_EXTRA_ENV_SETTINGS \ 95 "loadaddr=0x82000000\0" \ 96 "console=ttyO2,115200n8\0" \ 97 "mpurate=600\0" \ 98 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 99 "tv_mode=omapfb.mode=tv:ntsc\0" \ 100 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 101 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 102 "extra_options= \0" \ 103 "mmcdev=0\0" \ 104 "mmcroot=/dev/mmcblk0p2 rw\0" \ 105 "mmcrootfstype=ext3 rootwait\0" \ 106 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 107 "nandrootfstype=ubifs\0" \ 108 "mmcargs=setenv bootargs console=${console} " \ 109 "mpurate=${mpurate} " \ 110 "${video_mode} " \ 111 "root=${mmcroot} " \ 112 "rootfstype=${mmcrootfstype} " \ 113 "${extra_options}\0" \ 114 "nandargs=setenv bootargs console=${console} " \ 115 "mpurate=${mpurate} " \ 116 "${video_mode} " \ 117 "${network_setting} " \ 118 "root=${nandroot} " \ 119 "rootfstype=${nandrootfstype} "\ 120 "${extra_options}\0" \ 121 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 122 "bootscript=echo Running bootscript from mmc ...; " \ 123 "source ${loadaddr}\0" \ 124 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 125 "mmcboot=echo Booting from mmc ...; " \ 126 "run mmcargs; " \ 127 "bootm ${loadaddr}\0" \ 128 "nandboot=echo Booting from nand ...; " \ 129 "run nandargs; " \ 130 "nand read ${loadaddr} 280000 400000; " \ 131 "bootm ${loadaddr}\0" \ 132 133 #define CONFIG_BOOTCOMMAND \ 134 "if mmc rescan ${mmcdev}; then " \ 135 "if run loadbootscript; then " \ 136 "run bootscript; " \ 137 "else " \ 138 "if run loaduimage; then " \ 139 "run mmcboot; " \ 140 "else run nandboot; " \ 141 "fi; " \ 142 "fi; " \ 143 "else run nandboot; fi" 144 145 /* 146 * Miscellaneous configurable options 147 */ 148 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 149 150 /* turn on command-line edit/hist/auto */ 151 #define CONFIG_CMDLINE_EDITING 152 #define CONFIG_AUTO_COMPLETE 153 154 #define CONFIG_SYS_ALT_MEMTEST 1 155 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 156 /* defaults */ 157 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 158 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 159 160 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 161 /* load address */ 162 #define CONFIG_SYS_TEXT_BASE 0x80008000 163 164 /* 165 * OMAP3 has 12 GP timers, they can be driven by the system clock 166 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 167 * This rate is divided by a local divisor. 168 */ 169 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 170 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 171 172 /* 173 * Physical Memory Map 174 */ 175 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 176 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 177 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 178 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 179 180 /* 181 * FLASH and environment organization 182 */ 183 184 /* **** PISMO SUPPORT *** */ 185 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 186 #define CONFIG_SYS_FLASH_BASE NAND_BASE 187 188 /* Monitor at start of flash */ 189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 190 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 191 192 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 193 194 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 195 #define CONFIG_ENV_OFFSET 0x260000 196 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 197 198 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 199 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 200 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 201 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 202 CONFIG_SYS_INIT_RAM_SIZE - \ 203 GENERATED_GBL_DATA_SIZE) 204 205 /* 206 * USB 207 * 208 * Currently only EHCI is enabled, the MUSB OTG controller 209 * is not enabled. 210 */ 211 212 /* USB EHCI */ 213 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 214 215 /* Defines for SPL */ 216 #define CONFIG_SPL_FRAMEWORK 217 #define CONFIG_SPL_NAND_SIMPLE 218 219 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 220 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 221 222 #define CONFIG_SPL_NAND_BASE 223 #define CONFIG_SPL_NAND_DRIVERS 224 #define CONFIG_SPL_NAND_ECC 225 226 /* NAND boot config */ 227 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 228 #define CONFIG_SYS_NAND_PAGE_COUNT 64 229 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 230 #define CONFIG_SYS_NAND_OOBSIZE 64 231 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 232 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 233 /* 234 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 235 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 236 */ 237 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 238 10, 11, 12, 13 } 239 #define CONFIG_SYS_NAND_ECCSIZE 512 240 #define CONFIG_SYS_NAND_ECCBYTES 3 241 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 242 243 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 244 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 245 246 #define CONFIG_SPL_TEXT_BASE 0x40200800 247 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 248 CONFIG_SPL_TEXT_BASE) 249 250 /* 251 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 252 * older x-loader implementations. And move the BSS area so that it 253 * doesn't overlap with TEXT_BASE. 254 */ 255 #define CONFIG_SYS_TEXT_BASE 0x80008000 256 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 257 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 258 259 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 260 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 261 262 #endif /* __CONFIG_H */ 263