1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ 20 #define CONFIG_OMAP /* in a TI OMAP core */ 21 #define CONFIG_OMAP34XX /* which is a 34XX */ 22 23 #define CONFIG_OMAP_GPIO 24 #define CONFIG_OMAP_COMMON 25 26 #define MACH_TYPE_OMAP3_TAO3530 2836 27 28 #define CONFIG_SDRC /* Has an SDRC controller */ 29 30 #include <asm/arch/cpu.h> /* get chip and board defs */ 31 #include <asm/arch/omap3.h> 32 33 /* 34 * Display CPU and Board information 35 */ 36 #define CONFIG_DISPLAY_CPUINFO 37 #define CONFIG_DISPLAY_BOARDINFO 38 39 /* Clock Defines */ 40 #define V_OSCK 26000000 /* Clock output from T2 */ 41 #define V_SCLK (V_OSCK >> 1) 42 43 #define CONFIG_MISC_INIT_R 44 45 #define CONFIG_OF_LIBFDT 46 47 #define CONFIG_CMDLINE_TAG 48 #define CONFIG_SETUP_MEMORY_TAGS 49 #define CONFIG_INITRD_TAG 50 #define CONFIG_REVISION_TAG 51 52 /* 53 * Size of malloc() pool 54 */ 55 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 56 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 57 58 /* 59 * Hardware drivers 60 */ 61 62 /* 63 * NS16550 Configuration 64 */ 65 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 66 67 #define CONFIG_SYS_NS16550 68 #define CONFIG_SYS_NS16550_SERIAL 69 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 70 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 71 72 /* 73 * select serial console configuration 74 */ 75 #define CONFIG_CONS_INDEX 3 76 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 77 78 /* allow to overwrite serial and ethaddr */ 79 #define CONFIG_ENV_OVERWRITE 80 #define CONFIG_BAUDRATE 115200 81 #define CONFIG_GENERIC_MMC 82 #define CONFIG_MMC 83 #define CONFIG_OMAP_HSMMC 84 #define CONFIG_DOS_PARTITION 85 86 /* GPIO banks */ 87 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ 88 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ 89 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ 90 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ 91 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ 92 93 /* commands to include */ 94 #include <config_cmd_default.h> 95 96 #define CONFIG_CMD_CACHE 97 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 98 #define CONFIG_CMD_FAT /* FAT support */ 99 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 100 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 101 #define MTDIDS_DEFAULT "nand0=nand" 102 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 103 "1920k(u-boot),128k(u-boot-env),"\ 104 "4m(kernel),-(fs)" 105 106 #define CONFIG_CMD_I2C /* I2C serial bus support */ 107 #define CONFIG_CMD_MMC /* MMC support */ 108 #define CONFIG_CMD_NAND /* NAND support */ 109 #define CONFIG_CMD_DHCP 110 #define CONFIG_CMD_PING 111 112 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 113 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 114 #undef CONFIG_CMD_IMI /* iminfo */ 115 #undef CONFIG_CMD_IMLS /* List all found images */ 116 117 #define CONFIG_SYS_NO_FLASH 118 #define CONFIG_SYS_I2C 119 #define CONFIG_SYS_I2C_OMAP34XX 120 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 121 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 122 #define CONFIG_I2C_MULTI_BUS 123 124 /* 125 * TWL4030 126 */ 127 #define CONFIG_TWL4030_POWER 128 #define CONFIG_TWL4030_LED 129 130 /* 131 * Board NAND Info. 132 */ 133 #define CONFIG_SYS_NAND_QUIET_TEST 134 #define CONFIG_NAND_OMAP_GPMC 135 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 136 /* to access nand */ 137 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 138 /* to access nand at */ 139 /* CS0 */ 140 141 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 142 /* devices */ 143 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 144 /* Environment information */ 145 #define CONFIG_BOOTDELAY 3 146 147 #define CONFIG_EXTRA_ENV_SETTINGS \ 148 "loadaddr=0x82000000\0" \ 149 "console=ttyO2,115200n8\0" \ 150 "mpurate=600\0" \ 151 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 152 "tv_mode=omapfb.mode=tv:ntsc\0" \ 153 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 154 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 155 "extra_options= \0" \ 156 "mmcdev=0\0" \ 157 "mmcroot=/dev/mmcblk0p2 rw\0" \ 158 "mmcrootfstype=ext3 rootwait\0" \ 159 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 160 "nandrootfstype=ubifs\0" \ 161 "mmcargs=setenv bootargs console=${console} " \ 162 "mpurate=${mpurate} " \ 163 "${video_mode} " \ 164 "root=${mmcroot} " \ 165 "rootfstype=${mmcrootfstype} " \ 166 "${extra_options}\0" \ 167 "nandargs=setenv bootargs console=${console} " \ 168 "mpurate=${mpurate} " \ 169 "${video_mode} " \ 170 "${network_setting} " \ 171 "root=${nandroot} " \ 172 "rootfstype=${nandrootfstype} "\ 173 "${extra_options}\0" \ 174 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 175 "bootscript=echo Running bootscript from mmc ...; " \ 176 "source ${loadaddr}\0" \ 177 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 178 "mmcboot=echo Booting from mmc ...; " \ 179 "run mmcargs; " \ 180 "bootm ${loadaddr}\0" \ 181 "nandboot=echo Booting from nand ...; " \ 182 "run nandargs; " \ 183 "nand read ${loadaddr} 280000 400000; " \ 184 "bootm ${loadaddr}\0" \ 185 186 #define CONFIG_BOOTCOMMAND \ 187 "if mmc rescan ${mmcdev}; then " \ 188 "if run loadbootscript; then " \ 189 "run bootscript; " \ 190 "else " \ 191 "if run loaduimage; then " \ 192 "run mmcboot; " \ 193 "else run nandboot; " \ 194 "fi; " \ 195 "fi; " \ 196 "else run nandboot; fi" 197 198 /* 199 * Miscellaneous configurable options 200 */ 201 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 202 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 203 #define CONFIG_SYS_PROMPT "TAO-3530 # " 204 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 205 206 /* turn on command-line edit/hist/auto */ 207 #define CONFIG_CMDLINE_EDITING 208 #define CONFIG_COMMAND_HISTORY 209 #define CONFIG_AUTO_COMPLETE 210 211 /* Print Buffer Size */ 212 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 213 sizeof(CONFIG_SYS_PROMPT) + 16) 214 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 215 /* Boot Argument Buffer Size */ 216 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 217 218 #define CONFIG_SYS_ALT_MEMTEST 1 219 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 220 /* defaults */ 221 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 222 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 223 224 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 225 /* load address */ 226 #define CONFIG_SYS_TEXT_BASE 0x80008000 227 228 /* 229 * OMAP3 has 12 GP timers, they can be driven by the system clock 230 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 231 * This rate is divided by a local divisor. 232 */ 233 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 234 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 235 236 /* 237 * Stack sizes 238 * 239 * The stack sizes are set up in start.S using the settings below 240 */ 241 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 242 243 /* 244 * Physical Memory Map 245 */ 246 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 247 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 248 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 249 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 250 251 /* 252 * FLASH and environment organization 253 */ 254 255 /* **** PISMO SUPPORT *** */ 256 257 /* Configure the PISMO */ 258 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 259 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 260 261 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 262 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE 263 264 /* Monitor at start of flash */ 265 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 266 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 267 268 #define CONFIG_ENV_IS_IN_NAND 1 269 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 270 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 271 272 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 273 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 274 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 275 276 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 277 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 278 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 279 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 280 CONFIG_SYS_INIT_RAM_SIZE - \ 281 GENERATED_GBL_DATA_SIZE) 282 283 #define CONFIG_OMAP3_SPI 284 285 /* 286 * USB 287 * 288 * Currently only EHCI is enabled, the MUSB OTG controller 289 * is not enabled. 290 */ 291 292 /* USB EHCI */ 293 #define CONFIG_CMD_USB 294 #define CONFIG_USB_EHCI 295 #define CONFIG_USB_EHCI_OMAP 296 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 297 298 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 299 #define CONFIG_USB_HOST_ETHER 300 #define CONFIG_USB_ETHER_SMSC95XX 301 302 #define CONFIG_USB_ETHER 303 #define CONFIG_USB_ETHER_RNDIS 304 #define CONFIG_USB_STORAGE 305 #define CONGIG_CMD_STORAGE 306 307 /* Defines for SPL */ 308 #define CONFIG_SPL 309 #define CONFIG_SPL_FRAMEWORK 310 #define CONFIG_SPL_NAND_SIMPLE 311 312 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 313 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 314 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 315 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 316 317 #define CONFIG_SPL_BOARD_INIT 318 #define CONFIG_SPL_LIBCOMMON_SUPPORT 319 #define CONFIG_SPL_LIBDISK_SUPPORT 320 #define CONFIG_SPL_I2C_SUPPORT 321 #define CONFIG_SPL_LIBGENERIC_SUPPORT 322 #define CONFIG_SPL_MMC_SUPPORT 323 #define CONFIG_SPL_FAT_SUPPORT 324 #define CONFIG_SPL_SERIAL_SUPPORT 325 #define CONFIG_SPL_NAND_SUPPORT 326 #define CONFIG_SPL_NAND_BASE 327 #define CONFIG_SPL_NAND_DRIVERS 328 #define CONFIG_SPL_NAND_ECC 329 #define CONFIG_SPL_GPIO_SUPPORT 330 #define CONFIG_SPL_POWER_SUPPORT 331 #define CONFIG_SPL_OMAP3_ID_NAND 332 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 333 334 /* NAND boot config */ 335 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 336 #define CONFIG_SYS_NAND_PAGE_COUNT 64 337 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 338 #define CONFIG_SYS_NAND_OOBSIZE 64 339 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 340 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 341 /* 342 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 343 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 344 */ 345 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 346 10, 11, 12, 13 } 347 #define CONFIG_SYS_NAND_ECCSIZE 512 348 #define CONFIG_SYS_NAND_ECCBYTES 3 349 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 350 351 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 352 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 353 354 #define CONFIG_SPL_TEXT_BASE 0x40200800 355 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 356 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 357 358 /* 359 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 360 * older x-loader implementations. And move the BSS area so that it 361 * doesn't overlap with TEXT_BASE. 362 */ 363 #define CONFIG_SYS_TEXT_BASE 0x80008000 364 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 365 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 366 367 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 368 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 369 370 #endif /* __CONFIG_H */ 371