1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP /* in a TI OMAP core */ 20 21 #define CONFIG_OMAP_GPIO 22 #define CONFIG_OMAP_COMMON 23 #define CONFIG_SYS_GENERIC_BOARD 24 /* Common ARM Erratas */ 25 #define CONFIG_ARM_ERRATA_454179 26 #define CONFIG_ARM_ERRATA_430973 27 #define CONFIG_ARM_ERRATA_621766 28 29 #define MACH_TYPE_OMAP3_TAO3530 2836 30 31 #define CONFIG_SDRC /* Has an SDRC controller */ 32 33 #include <asm/arch/cpu.h> /* get chip and board defs */ 34 #include <asm/arch/omap.h> 35 36 /* 37 * Display CPU and Board information 38 */ 39 #define CONFIG_DISPLAY_CPUINFO 40 #define CONFIG_DISPLAY_BOARDINFO 41 42 /* Clock Defines */ 43 #define V_OSCK 26000000 /* Clock output from T2 */ 44 #define V_SCLK (V_OSCK >> 1) 45 46 #define CONFIG_MISC_INIT_R 47 48 #define CONFIG_OF_LIBFDT 49 50 #define CONFIG_CMDLINE_TAG 51 #define CONFIG_SETUP_MEMORY_TAGS 52 #define CONFIG_INITRD_TAG 53 #define CONFIG_REVISION_TAG 54 55 /* 56 * Size of malloc() pool 57 */ 58 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 59 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 60 61 /* 62 * Hardware drivers 63 */ 64 65 /* 66 * NS16550 Configuration 67 */ 68 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 69 70 #define CONFIG_SYS_NS16550 71 #define CONFIG_SYS_NS16550_SERIAL 72 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 73 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 74 75 /* 76 * select serial console configuration 77 */ 78 #define CONFIG_CONS_INDEX 3 79 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 80 81 /* allow to overwrite serial and ethaddr */ 82 #define CONFIG_ENV_OVERWRITE 83 #define CONFIG_BAUDRATE 115200 84 #define CONFIG_GENERIC_MMC 85 #define CONFIG_MMC 86 #define CONFIG_OMAP_HSMMC 87 #define CONFIG_DOS_PARTITION 88 89 /* GPIO banks */ 90 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ 91 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ 92 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ 93 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ 94 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ 95 96 /* commands to include */ 97 #define CONFIG_CMD_CACHE 98 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 99 #define CONFIG_CMD_FAT /* FAT support */ 100 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 101 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 102 #define MTDIDS_DEFAULT "nand0=nand" 103 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 104 "1920k(u-boot),128k(u-boot-env),"\ 105 "4m(kernel),-(fs)" 106 107 #define CONFIG_CMD_I2C /* I2C serial bus support */ 108 #define CONFIG_CMD_MMC /* MMC support */ 109 #define CONFIG_CMD_NAND /* NAND support */ 110 #define CONFIG_CMD_DHCP 111 #define CONFIG_CMD_PING 112 113 #define CONFIG_SYS_NO_FLASH 114 #define CONFIG_SYS_I2C 115 #define CONFIG_SYS_I2C_OMAP34XX 116 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 117 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 118 #define CONFIG_I2C_MULTI_BUS 119 120 /* 121 * TWL4030 122 */ 123 #define CONFIG_TWL4030_POWER 124 #define CONFIG_TWL4030_LED 125 126 /* 127 * Board NAND Info. 128 */ 129 #define CONFIG_SYS_NAND_QUIET_TEST 130 #define CONFIG_NAND_OMAP_GPMC 131 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 132 /* to access nand */ 133 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 134 /* to access nand at */ 135 /* CS0 */ 136 137 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 138 /* devices */ 139 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 140 /* Environment information */ 141 #define CONFIG_BOOTDELAY 3 142 143 #define CONFIG_EXTRA_ENV_SETTINGS \ 144 "loadaddr=0x82000000\0" \ 145 "console=ttyO2,115200n8\0" \ 146 "mpurate=600\0" \ 147 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 148 "tv_mode=omapfb.mode=tv:ntsc\0" \ 149 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 150 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 151 "extra_options= \0" \ 152 "mmcdev=0\0" \ 153 "mmcroot=/dev/mmcblk0p2 rw\0" \ 154 "mmcrootfstype=ext3 rootwait\0" \ 155 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 156 "nandrootfstype=ubifs\0" \ 157 "mmcargs=setenv bootargs console=${console} " \ 158 "mpurate=${mpurate} " \ 159 "${video_mode} " \ 160 "root=${mmcroot} " \ 161 "rootfstype=${mmcrootfstype} " \ 162 "${extra_options}\0" \ 163 "nandargs=setenv bootargs console=${console} " \ 164 "mpurate=${mpurate} " \ 165 "${video_mode} " \ 166 "${network_setting} " \ 167 "root=${nandroot} " \ 168 "rootfstype=${nandrootfstype} "\ 169 "${extra_options}\0" \ 170 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 171 "bootscript=echo Running bootscript from mmc ...; " \ 172 "source ${loadaddr}\0" \ 173 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 174 "mmcboot=echo Booting from mmc ...; " \ 175 "run mmcargs; " \ 176 "bootm ${loadaddr}\0" \ 177 "nandboot=echo Booting from nand ...; " \ 178 "run nandargs; " \ 179 "nand read ${loadaddr} 280000 400000; " \ 180 "bootm ${loadaddr}\0" \ 181 182 #define CONFIG_BOOTCOMMAND \ 183 "if mmc rescan ${mmcdev}; then " \ 184 "if run loadbootscript; then " \ 185 "run bootscript; " \ 186 "else " \ 187 "if run loaduimage; then " \ 188 "run mmcboot; " \ 189 "else run nandboot; " \ 190 "fi; " \ 191 "fi; " \ 192 "else run nandboot; fi" 193 194 /* 195 * Miscellaneous configurable options 196 */ 197 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 198 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 199 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 200 201 /* turn on command-line edit/hist/auto */ 202 #define CONFIG_CMDLINE_EDITING 203 #define CONFIG_COMMAND_HISTORY 204 #define CONFIG_AUTO_COMPLETE 205 206 /* Print Buffer Size */ 207 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 208 sizeof(CONFIG_SYS_PROMPT) + 16) 209 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 210 /* Boot Argument Buffer Size */ 211 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 212 213 #define CONFIG_SYS_ALT_MEMTEST 1 214 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 215 /* defaults */ 216 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 217 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 218 219 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 220 /* load address */ 221 #define CONFIG_SYS_TEXT_BASE 0x80008000 222 223 /* 224 * OMAP3 has 12 GP timers, they can be driven by the system clock 225 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 226 * This rate is divided by a local divisor. 227 */ 228 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 229 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 230 231 /* 232 * Stack sizes 233 * 234 * The stack sizes are set up in start.S using the settings below 235 */ 236 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 237 238 /* 239 * Physical Memory Map 240 */ 241 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 242 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 243 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 244 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 245 246 /* 247 * FLASH and environment organization 248 */ 249 250 /* **** PISMO SUPPORT *** */ 251 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 252 #define CONFIG_SYS_FLASH_BASE NAND_BASE 253 254 /* Monitor at start of flash */ 255 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 256 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 257 258 #define CONFIG_ENV_IS_IN_NAND 1 259 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 260 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 261 262 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 263 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 264 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 265 266 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 267 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 268 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 269 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 270 CONFIG_SYS_INIT_RAM_SIZE - \ 271 GENERATED_GBL_DATA_SIZE) 272 273 #define CONFIG_OMAP3_SPI 274 275 /* 276 * USB 277 * 278 * Currently only EHCI is enabled, the MUSB OTG controller 279 * is not enabled. 280 */ 281 282 /* USB EHCI */ 283 #define CONFIG_CMD_USB 284 #define CONFIG_USB_EHCI 285 #define CONFIG_USB_EHCI_OMAP 286 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 287 288 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 289 #define CONFIG_USB_HOST_ETHER 290 #define CONFIG_USB_ETHER_SMSC95XX 291 292 #define CONFIG_USB_ETHER 293 #define CONFIG_USB_ETHER_RNDIS 294 #define CONFIG_USB_STORAGE 295 #define CONGIG_CMD_STORAGE 296 297 /* Defines for SPL */ 298 #define CONFIG_SPL_FRAMEWORK 299 #define CONFIG_SPL_NAND_SIMPLE 300 301 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 302 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 303 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 304 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 305 306 #define CONFIG_SPL_BOARD_INIT 307 #define CONFIG_SPL_LIBCOMMON_SUPPORT 308 #define CONFIG_SPL_LIBDISK_SUPPORT 309 #define CONFIG_SPL_I2C_SUPPORT 310 #define CONFIG_SPL_LIBGENERIC_SUPPORT 311 #define CONFIG_SPL_MMC_SUPPORT 312 #define CONFIG_SPL_FAT_SUPPORT 313 #define CONFIG_SPL_SERIAL_SUPPORT 314 #define CONFIG_SPL_NAND_SUPPORT 315 #define CONFIG_SPL_NAND_BASE 316 #define CONFIG_SPL_NAND_DRIVERS 317 #define CONFIG_SPL_NAND_ECC 318 #define CONFIG_SPL_GPIO_SUPPORT 319 #define CONFIG_SPL_POWER_SUPPORT 320 #define CONFIG_SPL_OMAP3_ID_NAND 321 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 322 323 /* NAND boot config */ 324 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 325 #define CONFIG_SYS_NAND_PAGE_COUNT 64 326 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 327 #define CONFIG_SYS_NAND_OOBSIZE 64 328 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 329 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 330 /* 331 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 332 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 333 */ 334 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 335 10, 11, 12, 13 } 336 #define CONFIG_SYS_NAND_ECCSIZE 512 337 #define CONFIG_SYS_NAND_ECCBYTES 3 338 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 339 340 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 341 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 342 343 #define CONFIG_SPL_TEXT_BASE 0x40200800 344 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 345 346 /* 347 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 348 * older x-loader implementations. And move the BSS area so that it 349 * doesn't overlap with TEXT_BASE. 350 */ 351 #define CONFIG_SYS_TEXT_BASE 0x80008000 352 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 353 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 354 355 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 356 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 357 358 #endif /* __CONFIG_H */ 359