1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP /* in a TI OMAP core */ 20 21 #define CONFIG_OMAP_GPIO 22 /* Common ARM Erratas */ 23 #define CONFIG_ARM_ERRATA_454179 24 #define CONFIG_ARM_ERRATA_430973 25 #define CONFIG_ARM_ERRATA_621766 26 27 #define CONFIG_SDRC /* Has an SDRC controller */ 28 29 #include <asm/arch/cpu.h> /* get chip and board defs */ 30 #include <asm/arch/omap.h> 31 32 /* Clock Defines */ 33 #define V_OSCK 26000000 /* Clock output from T2 */ 34 #define V_SCLK (V_OSCK >> 1) 35 36 #define CONFIG_MISC_INIT_R 37 38 #define CONFIG_CMDLINE_TAG 39 #define CONFIG_SETUP_MEMORY_TAGS 40 #define CONFIG_INITRD_TAG 41 #define CONFIG_REVISION_TAG 42 43 /* 44 * Size of malloc() pool 45 */ 46 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 47 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 48 49 /* 50 * Hardware drivers 51 */ 52 53 /* 54 * NS16550 Configuration 55 */ 56 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 57 58 #define CONFIG_SYS_NS16550_SERIAL 59 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 60 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 61 62 /* 63 * select serial console configuration 64 */ 65 #define CONFIG_CONS_INDEX 3 66 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 67 68 /* allow to overwrite serial and ethaddr */ 69 #define CONFIG_ENV_OVERWRITE 70 #define CONFIG_BAUDRATE 115200 71 #define CONFIG_GENERIC_MMC 72 73 /* GPIO banks */ 74 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ 75 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ 76 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ 77 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ 78 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ 79 80 /* commands to include */ 81 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 82 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 83 #define MTDIDS_DEFAULT "nand0=nand" 84 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 85 "1920k(u-boot),128k(u-boot-env),"\ 86 "4m(kernel),-(fs)" 87 88 #define CONFIG_CMD_NAND /* NAND support */ 89 90 #define CONFIG_SYS_NO_FLASH 91 #define CONFIG_SYS_I2C 92 #define CONFIG_SYS_I2C_OMAP34XX 93 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 94 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 95 #define CONFIG_I2C_MULTI_BUS 96 97 /* 98 * TWL4030 99 */ 100 #define CONFIG_TWL4030_POWER 101 #define CONFIG_TWL4030_LED 102 103 /* 104 * Board NAND Info. 105 */ 106 #define CONFIG_NAND_OMAP_GPMC 107 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 108 /* to access nand */ 109 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 110 /* to access nand at */ 111 /* CS0 */ 112 113 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 114 /* devices */ 115 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 116 /* Environment information */ 117 118 #define CONFIG_EXTRA_ENV_SETTINGS \ 119 "loadaddr=0x82000000\0" \ 120 "console=ttyO2,115200n8\0" \ 121 "mpurate=600\0" \ 122 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 123 "tv_mode=omapfb.mode=tv:ntsc\0" \ 124 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 125 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 126 "extra_options= \0" \ 127 "mmcdev=0\0" \ 128 "mmcroot=/dev/mmcblk0p2 rw\0" \ 129 "mmcrootfstype=ext3 rootwait\0" \ 130 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 131 "nandrootfstype=ubifs\0" \ 132 "mmcargs=setenv bootargs console=${console} " \ 133 "mpurate=${mpurate} " \ 134 "${video_mode} " \ 135 "root=${mmcroot} " \ 136 "rootfstype=${mmcrootfstype} " \ 137 "${extra_options}\0" \ 138 "nandargs=setenv bootargs console=${console} " \ 139 "mpurate=${mpurate} " \ 140 "${video_mode} " \ 141 "${network_setting} " \ 142 "root=${nandroot} " \ 143 "rootfstype=${nandrootfstype} "\ 144 "${extra_options}\0" \ 145 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 146 "bootscript=echo Running bootscript from mmc ...; " \ 147 "source ${loadaddr}\0" \ 148 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 149 "mmcboot=echo Booting from mmc ...; " \ 150 "run mmcargs; " \ 151 "bootm ${loadaddr}\0" \ 152 "nandboot=echo Booting from nand ...; " \ 153 "run nandargs; " \ 154 "nand read ${loadaddr} 280000 400000; " \ 155 "bootm ${loadaddr}\0" \ 156 157 #define CONFIG_BOOTCOMMAND \ 158 "if mmc rescan ${mmcdev}; then " \ 159 "if run loadbootscript; then " \ 160 "run bootscript; " \ 161 "else " \ 162 "if run loaduimage; then " \ 163 "run mmcboot; " \ 164 "else run nandboot; " \ 165 "fi; " \ 166 "fi; " \ 167 "else run nandboot; fi" 168 169 /* 170 * Miscellaneous configurable options 171 */ 172 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 173 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 174 175 /* turn on command-line edit/hist/auto */ 176 #define CONFIG_CMDLINE_EDITING 177 #define CONFIG_COMMAND_HISTORY 178 #define CONFIG_AUTO_COMPLETE 179 180 /* Print Buffer Size */ 181 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 182 sizeof(CONFIG_SYS_PROMPT) + 16) 183 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 184 /* Boot Argument Buffer Size */ 185 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 186 187 #define CONFIG_SYS_ALT_MEMTEST 1 188 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 189 /* defaults */ 190 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 191 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 192 193 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 194 /* load address */ 195 #define CONFIG_SYS_TEXT_BASE 0x80008000 196 197 /* 198 * OMAP3 has 12 GP timers, they can be driven by the system clock 199 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 200 * This rate is divided by a local divisor. 201 */ 202 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 203 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 204 205 /* 206 * Stack sizes 207 * 208 * The stack sizes are set up in start.S using the settings below 209 */ 210 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 211 212 /* 213 * Physical Memory Map 214 */ 215 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 216 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 217 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 218 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 219 220 /* 221 * FLASH and environment organization 222 */ 223 224 /* **** PISMO SUPPORT *** */ 225 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 226 #define CONFIG_SYS_FLASH_BASE NAND_BASE 227 228 /* Monitor at start of flash */ 229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 230 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 231 232 #define CONFIG_ENV_IS_IN_NAND 1 233 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 234 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 235 236 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 237 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 238 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 239 240 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 241 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 242 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 243 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 244 CONFIG_SYS_INIT_RAM_SIZE - \ 245 GENERATED_GBL_DATA_SIZE) 246 247 #define CONFIG_OMAP3_SPI 248 249 /* 250 * USB 251 * 252 * Currently only EHCI is enabled, the MUSB OTG controller 253 * is not enabled. 254 */ 255 256 /* USB EHCI */ 257 #define CONFIG_USB_EHCI 258 #define CONFIG_USB_EHCI_OMAP 259 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 260 261 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 262 #define CONFIG_USB_HOST_ETHER 263 #define CONFIG_USB_ETHER_SMSC95XX 264 265 #define CONFIG_USB_ETHER 266 #define CONFIG_USB_ETHER_RNDIS 267 #define CONGIG_CMD_STORAGE 268 269 /* Defines for SPL */ 270 #define CONFIG_SPL_FRAMEWORK 271 #define CONFIG_SPL_NAND_SIMPLE 272 273 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 274 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 275 276 #define CONFIG_SPL_BOARD_INIT 277 #define CONFIG_SPL_NAND_BASE 278 #define CONFIG_SPL_NAND_DRIVERS 279 #define CONFIG_SPL_NAND_ECC 280 #define CONFIG_SPL_OMAP3_ID_NAND 281 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 282 283 /* NAND boot config */ 284 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 285 #define CONFIG_SYS_NAND_PAGE_COUNT 64 286 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 287 #define CONFIG_SYS_NAND_OOBSIZE 64 288 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 289 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 290 /* 291 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 292 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 293 */ 294 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 295 10, 11, 12, 13 } 296 #define CONFIG_SYS_NAND_ECCSIZE 512 297 #define CONFIG_SYS_NAND_ECCBYTES 3 298 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 299 300 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 301 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 302 303 #define CONFIG_SPL_TEXT_BASE 0x40200800 304 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 305 CONFIG_SPL_TEXT_BASE) 306 307 /* 308 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 309 * older x-loader implementations. And move the BSS area so that it 310 * doesn't overlap with TEXT_BASE. 311 */ 312 #define CONFIG_SYS_TEXT_BASE 0x80008000 313 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 314 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 315 316 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 317 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 318 319 #endif /* __CONFIG_H */ 320