xref: /openbmc/u-boot/include/configs/tao3530.h (revision 8aa42441)
1 /*
2  * Configuration settings for the TechNexion TAO-3530 SOM
3  * equipped on Thunder baseboard.
4  *
5  * Edward Lin <linuxfae@technexion.com>
6  * Tapani Utriainen <linuxfae@technexion.com>
7  *
8  * Copyright (C) 2013 Stefan Roese <sr@denx.de>
9  *
10  * SPDX-License-Identifier:	GPL-2.0+
11  */
12 
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15 
16 /*
17  * High Level Configuration Options
18  */
19 #define CONFIG_ARMV7			/* This is an ARM V7 CPU core */
20 #define CONFIG_OMAP			/* in a TI OMAP core */
21 #define CONFIG_OMAP34XX			/* which is a 34XX */
22 
23 #define CONFIG_OMAP_GPIO
24 #define CONFIG_OMAP_COMMON
25 
26 #define MACH_TYPE_OMAP3_TAO3530		2836
27 
28 #define CONFIG_SDRC			/* Has an SDRC controller */
29 
30 #include <asm/arch/cpu.h>		/* get chip and board defs */
31 #include <asm/arch/omap3.h>
32 
33 /*
34  * Display CPU and Board information
35  */
36 #define CONFIG_DISPLAY_CPUINFO
37 #define CONFIG_DISPLAY_BOARDINFO
38 
39 /* Clock Defines */
40 #define V_OSCK			26000000	/* Clock output from T2 */
41 #define V_SCLK			(V_OSCK >> 1)
42 
43 #define CONFIG_MISC_INIT_R
44 
45 #define CONFIG_OF_LIBFDT
46 
47 #define CONFIG_CMDLINE_TAG
48 #define CONFIG_SETUP_MEMORY_TAGS
49 #define CONFIG_INITRD_TAG
50 #define CONFIG_REVISION_TAG
51 
52 /*
53  * Size of malloc() pool
54  */
55 #define CONFIG_SYS_MALLOC_LEN		(4 << 20)
56 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
57 
58 /*
59  * Hardware drivers
60  */
61 
62 /*
63  * NS16550 Configuration
64  */
65 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
66 
67 #define CONFIG_SYS_NS16550
68 #define CONFIG_SYS_NS16550_SERIAL
69 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
70 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
71 
72 /*
73  * select serial console configuration
74  */
75 #define CONFIG_CONS_INDEX		3
76 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
77 
78 /* allow to overwrite serial and ethaddr */
79 #define CONFIG_ENV_OVERWRITE
80 #define CONFIG_BAUDRATE			115200
81 #define CONFIG_GENERIC_MMC
82 #define CONFIG_MMC
83 #define CONFIG_OMAP_HSMMC
84 #define CONFIG_DOS_PARTITION
85 
86 /* commands to include */
87 #include <config_cmd_default.h>
88 
89 #define CONFIG_CMD_CACHE
90 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
91 #define CONFIG_CMD_FAT		/* FAT support			*/
92 #define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
93 #define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
94 #define MTDIDS_DEFAULT			"nand0=nand"
95 #define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
96 					"1920k(u-boot),128k(u-boot-env),"\
97 					"4m(kernel),-(fs)"
98 
99 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
100 #define CONFIG_CMD_MMC		/* MMC support			*/
101 #define CONFIG_CMD_NAND		/* NAND support			*/
102 #define CONFIG_CMD_DHCP
103 #define CONFIG_CMD_PING
104 
105 #undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
106 #undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
107 #undef CONFIG_CMD_IMI		/* iminfo			*/
108 #undef CONFIG_CMD_IMLS		/* List all found images	*/
109 
110 #define CONFIG_SYS_NO_FLASH
111 #define CONFIG_SYS_I2C
112 #define CONFIG_SYS_I2C_OMAP34XX
113 #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
114 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
115 #define CONFIG_I2C_MULTI_BUS
116 
117 /*
118  * TWL4030
119  */
120 #define CONFIG_TWL4030_POWER
121 #define CONFIG_TWL4030_LED
122 
123 /*
124  * Board NAND Info.
125  */
126 #define CONFIG_SYS_NAND_QUIET_TEST
127 #define CONFIG_NAND_OMAP_GPMC
128 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
129 							/* to access nand */
130 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
131 							/* to access nand at */
132 							/* CS0 */
133 #define GPMC_NAND_ECC_LP_x16_LAYOUT
134 
135 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
136 							/* devices */
137 /* Environment information */
138 #define CONFIG_BOOTDELAY		3
139 
140 #define CONFIG_EXTRA_ENV_SETTINGS \
141 	"loadaddr=0x82000000\0" \
142 	"console=ttyO2,115200n8\0" \
143 	"mpurate=600\0" \
144 	"dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
145 	"tv_mode=omapfb.mode=tv:ntsc\0" \
146 	"video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
147 	"lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
148 	"extra_options= \0" \
149 	"mmcdev=0\0" \
150 	"mmcroot=/dev/mmcblk0p2 rw\0" \
151 	"mmcrootfstype=ext3 rootwait\0" \
152 	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
153 	"nandrootfstype=ubifs\0" \
154 	"mmcargs=setenv bootargs console=${console} " \
155 		"mpurate=${mpurate} " \
156 		"${video_mode} " \
157 		"root=${mmcroot} " \
158 		"rootfstype=${mmcrootfstype} " \
159 		"${extra_options}\0" \
160 	"nandargs=setenv bootargs console=${console} " \
161 		"mpurate=${mpurate} " \
162 		"${video_mode} " \
163 		"${network_setting} " \
164 		"root=${nandroot} " \
165 		"rootfstype=${nandrootfstype} "\
166 		"${extra_options}\0" \
167 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
168 	"bootscript=echo Running bootscript from mmc ...; " \
169 		"source ${loadaddr}\0" \
170 	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
171 	"mmcboot=echo Booting from mmc ...; " \
172 		"run mmcargs; " \
173 		"bootm ${loadaddr}\0" \
174 	"nandboot=echo Booting from nand ...; " \
175 		"run nandargs; " \
176 		"nand read ${loadaddr} 280000 400000; " \
177 		"bootm ${loadaddr}\0" \
178 
179 #define CONFIG_BOOTCOMMAND \
180 	"if mmc rescan ${mmcdev}; then " \
181 		"if run loadbootscript; then " \
182 			"run bootscript; " \
183 		"else " \
184 			"if run loaduimage; then " \
185 				"run mmcboot; " \
186 			"else run nandboot; " \
187 			"fi; " \
188 		"fi; " \
189 	"else run nandboot; fi"
190 
191 /*
192  * Miscellaneous configurable options
193  */
194 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
195 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
196 #define CONFIG_SYS_PROMPT		"TAO-3530 # "
197 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
198 
199 /* turn on command-line edit/hist/auto */
200 #define CONFIG_CMDLINE_EDITING
201 #define CONFIG_COMMAND_HISTORY
202 #define CONFIG_AUTO_COMPLETE
203 
204 /* Print Buffer Size */
205 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
206 					sizeof(CONFIG_SYS_PROMPT) + 16)
207 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
208 /* Boot Argument Buffer Size */
209 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
210 
211 #define CONFIG_SYS_ALT_MEMTEST		1
212 #define CONFIG_SYS_MEMTEST_START	(0x82000000)		/* memtest */
213 								/* defaults */
214 #define CONFIG_SYS_MEMTEST_END		(0x83FFFFFF)		/* 64MB */
215 #define CONFIG_SYS_MEMTEST_SCRATCH	(0x81000000)	/* dummy address */
216 
217 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
218 							/* load address */
219 #define CONFIG_SYS_TEXT_BASE		0x80008000
220 
221 /*
222  * OMAP3 has 12 GP timers, they can be driven by the system clock
223  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
224  * This rate is divided by a local divisor.
225  */
226 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
227 #define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
228 
229 /*
230  * Stack sizes
231  *
232  * The stack sizes are set up in start.S using the settings below
233  */
234 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
235 
236 /*
237  * Physical Memory Map
238  */
239 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
240 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
241 #define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
242 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
243 
244 /*
245  * FLASH and environment organization
246  */
247 
248 /* **** PISMO SUPPORT *** */
249 
250 /* Configure the PISMO */
251 #define PISMO1_NAND_SIZE		GPMC_SIZE_128M
252 #define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
253 
254 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
255 #define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
256 
257 /* Monitor at start of flash */
258 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
259 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
260 
261 #define CONFIG_ENV_IS_IN_NAND		1
262 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
263 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
264 
265 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)
266 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
267 #define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET
268 
269 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
270 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
271 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
272 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
273 					 CONFIG_SYS_INIT_RAM_SIZE - \
274 					 GENERATED_GBL_DATA_SIZE)
275 
276 #define CONFIG_OMAP3_SPI
277 
278 /*
279  * USB
280  *
281  * Currently only EHCI is enabled, the MUSB OTG controller
282  * is not enabled.
283  */
284 
285 /* USB EHCI */
286 #define CONFIG_CMD_USB
287 #define CONFIG_USB_EHCI
288 #define CONFIG_USB_EHCI_OMAP
289 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	162
290 
291 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
292 #define CONFIG_USB_HOST_ETHER
293 #define CONFIG_USB_ETHER_SMSC95XX
294 
295 #define CONFIG_USB_ETHER
296 #define CONFIG_USB_ETHER_RNDIS
297 #define CONFIG_USB_STORAGE
298 #define CONGIG_CMD_STORAGE
299 
300 /* Defines for SPL */
301 #define CONFIG_SPL
302 #define CONFIG_SPL_FRAMEWORK
303 #define CONFIG_SPL_NAND_SIMPLE
304 
305 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
306 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
307 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
308 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
309 
310 #define CONFIG_SPL_BOARD_INIT
311 #define CONFIG_SPL_LIBCOMMON_SUPPORT
312 #define CONFIG_SPL_LIBDISK_SUPPORT
313 #define CONFIG_SPL_I2C_SUPPORT
314 #define CONFIG_SPL_LIBGENERIC_SUPPORT
315 #define CONFIG_SPL_MMC_SUPPORT
316 #define CONFIG_SPL_FAT_SUPPORT
317 #define CONFIG_SPL_SERIAL_SUPPORT
318 #define CONFIG_SPL_NAND_SUPPORT
319 #define CONFIG_SPL_NAND_BASE
320 #define CONFIG_SPL_NAND_DRIVERS
321 #define CONFIG_SPL_NAND_ECC
322 #define CONFIG_SPL_GPIO_SUPPORT
323 #define CONFIG_SPL_POWER_SUPPORT
324 #define CONFIG_SPL_OMAP3_ID_NAND
325 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
326 
327 /* NAND boot config */
328 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
329 #define CONFIG_SYS_NAND_PAGE_COUNT	64
330 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
331 #define CONFIG_SYS_NAND_OOBSIZE		64
332 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
333 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
334 /*
335  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
336  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
337  */
338 #define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
339 					 10, 11, 12, 13 }
340 #define CONFIG_SYS_NAND_ECCSIZE		512
341 #define CONFIG_SYS_NAND_ECCBYTES	3
342 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
343 
344 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
345 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
346 
347 #define CONFIG_SPL_TEXT_BASE		0x40200800
348 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
349 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
350 
351 /*
352  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
353  * older x-loader implementations. And move the BSS area so that it
354  * doesn't overlap with TEXT_BASE.
355  */
356 #define CONFIG_SYS_TEXT_BASE		0x80008000
357 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
358 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
359 
360 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
361 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
362 
363 #endif /* __CONFIG_H */
364