1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuration settings for the TechNexion TAO-3530 SOM 4 * equipped on Thunder baseboard. 5 * 6 * Edward Lin <linuxfae@technexion.com> 7 * Tapani Utriainen <linuxfae@technexion.com> 8 * 9 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 19 #include <asm/arch/cpu.h> /* get chip and board defs */ 20 #include <asm/arch/omap.h> 21 22 /* Clock Defines */ 23 #define V_OSCK 26000000 /* Clock output from T2 */ 24 #define V_SCLK (V_OSCK >> 1) 25 26 #define CONFIG_MISC_INIT_R 27 28 #define CONFIG_CMDLINE_TAG 29 #define CONFIG_SETUP_MEMORY_TAGS 30 #define CONFIG_INITRD_TAG 31 #define CONFIG_REVISION_TAG 32 33 /* 34 * Size of malloc() pool 35 */ 36 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 37 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 38 39 /* 40 * Hardware drivers 41 */ 42 43 /* 44 * NS16550 Configuration 45 */ 46 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 47 48 #define CONFIG_SYS_NS16550_SERIAL 49 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 50 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 51 52 /* 53 * select serial console configuration 54 */ 55 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 56 57 /* allow to overwrite serial and ethaddr */ 58 #define CONFIG_ENV_OVERWRITE 59 60 /* commands to include */ 61 62 #define CONFIG_SYS_I2C 63 #define CONFIG_I2C_MULTI_BUS 64 65 /* 66 * TWL4030 67 */ 68 #define CONFIG_TWL4030_LED 69 70 /* 71 * Board NAND Info. 72 */ 73 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 74 /* to access nand */ 75 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 76 /* to access nand at */ 77 /* CS0 */ 78 79 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 80 /* devices */ 81 /* Environment information */ 82 83 #define CONFIG_EXTRA_ENV_SETTINGS \ 84 "loadaddr=0x82000000\0" \ 85 "console=ttyO2,115200n8\0" \ 86 "mpurate=600\0" \ 87 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 88 "tv_mode=omapfb.mode=tv:ntsc\0" \ 89 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 90 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 91 "extra_options= \0" \ 92 "mmcdev=0\0" \ 93 "mmcroot=/dev/mmcblk0p2 rw\0" \ 94 "mmcrootfstype=ext3 rootwait\0" \ 95 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 96 "nandrootfstype=ubifs\0" \ 97 "mmcargs=setenv bootargs console=${console} " \ 98 "mpurate=${mpurate} " \ 99 "${video_mode} " \ 100 "root=${mmcroot} " \ 101 "rootfstype=${mmcrootfstype} " \ 102 "${extra_options}\0" \ 103 "nandargs=setenv bootargs console=${console} " \ 104 "mpurate=${mpurate} " \ 105 "${video_mode} " \ 106 "${network_setting} " \ 107 "root=${nandroot} " \ 108 "rootfstype=${nandrootfstype} "\ 109 "${extra_options}\0" \ 110 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 111 "bootscript=echo Running bootscript from mmc ...; " \ 112 "source ${loadaddr}\0" \ 113 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 114 "mmcboot=echo Booting from mmc ...; " \ 115 "run mmcargs; " \ 116 "bootm ${loadaddr}\0" \ 117 "nandboot=echo Booting from nand ...; " \ 118 "run nandargs; " \ 119 "nand read ${loadaddr} 280000 400000; " \ 120 "bootm ${loadaddr}\0" \ 121 122 #define CONFIG_BOOTCOMMAND \ 123 "if mmc rescan ${mmcdev}; then " \ 124 "if run loadbootscript; then " \ 125 "run bootscript; " \ 126 "else " \ 127 "if run loaduimage; then " \ 128 "run mmcboot; " \ 129 "else run nandboot; " \ 130 "fi; " \ 131 "fi; " \ 132 "else run nandboot; fi" 133 134 /* 135 * Miscellaneous configurable options 136 */ 137 138 /* turn on command-line edit/hist/auto */ 139 140 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 141 /* defaults */ 142 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 143 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 144 145 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 146 /* load address */ 147 148 /* 149 * OMAP3 has 12 GP timers, they can be driven by the system clock 150 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 151 * This rate is divided by a local divisor. 152 */ 153 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 154 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 155 156 /* 157 * Physical Memory Map 158 */ 159 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 160 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 161 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 162 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 163 164 /* 165 * FLASH and environment organization 166 */ 167 168 /* **** PISMO SUPPORT *** */ 169 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 170 #define CONFIG_SYS_FLASH_BASE NAND_BASE 171 172 /* Monitor at start of flash */ 173 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 174 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 175 176 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 177 178 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 179 #define CONFIG_ENV_OFFSET 0x260000 180 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 181 182 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 183 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 184 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 185 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 186 CONFIG_SYS_INIT_RAM_SIZE - \ 187 GENERATED_GBL_DATA_SIZE) 188 189 /* 190 * USB 191 * 192 * Currently only EHCI is enabled, the MUSB OTG controller 193 * is not enabled. 194 */ 195 196 /* USB EHCI */ 197 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 198 199 /* Defines for SPL */ 200 201 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 202 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 203 204 #define CONFIG_SPL_NAND_BASE 205 #define CONFIG_SPL_NAND_DRIVERS 206 #define CONFIG_SPL_NAND_ECC 207 208 /* NAND boot config */ 209 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 210 #define CONFIG_SYS_NAND_PAGE_COUNT 64 211 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 212 #define CONFIG_SYS_NAND_OOBSIZE 64 213 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 214 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 215 /* 216 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 217 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 218 */ 219 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 220 10, 11, 12, 13 } 221 #define CONFIG_SYS_NAND_ECCSIZE 512 222 #define CONFIG_SYS_NAND_ECCBYTES 3 223 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 224 225 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 226 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 227 228 #define CONFIG_SPL_TEXT_BASE 0x40200800 229 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 230 CONFIG_SPL_TEXT_BASE) 231 232 /* 233 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 234 * older x-loader implementations. And move the BSS area so that it 235 * doesn't overlap with TEXT_BASE. 236 */ 237 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 238 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 239 240 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 241 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 242 243 #endif /* __CONFIG_H */ 244