1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuration settings for the TechNexion TAO-3530 SOM 4 * equipped on Thunder baseboard. 5 * 6 * Edward Lin <linuxfae@technexion.com> 7 * Tapani Utriainen <linuxfae@technexion.com> 8 * 9 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 19 #include <asm/arch/cpu.h> /* get chip and board defs */ 20 #include <asm/arch/omap.h> 21 22 /* Clock Defines */ 23 #define V_OSCK 26000000 /* Clock output from T2 */ 24 #define V_SCLK (V_OSCK >> 1) 25 26 #define CONFIG_MISC_INIT_R 27 28 #define CONFIG_CMDLINE_TAG 29 #define CONFIG_SETUP_MEMORY_TAGS 30 #define CONFIG_INITRD_TAG 31 #define CONFIG_REVISION_TAG 32 33 /* 34 * Size of malloc() pool 35 */ 36 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 37 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 38 39 /* 40 * Hardware drivers 41 */ 42 43 /* 44 * NS16550 Configuration 45 */ 46 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 47 48 #define CONFIG_SYS_NS16550_SERIAL 49 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 50 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 51 52 /* 53 * select serial console configuration 54 */ 55 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 56 57 /* allow to overwrite serial and ethaddr */ 58 #define CONFIG_ENV_OVERWRITE 59 60 /* commands to include */ 61 62 #define CONFIG_SYS_I2C 63 #define CONFIG_I2C_MULTI_BUS 64 65 /* 66 * TWL4030 67 */ 68 #define CONFIG_TWL4030_LED 69 70 /* 71 * Board NAND Info. 72 */ 73 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 74 /* to access nand at */ 75 /* CS0 */ 76 77 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 78 /* devices */ 79 /* Environment information */ 80 81 #define CONFIG_EXTRA_ENV_SETTINGS \ 82 "loadaddr=0x82000000\0" \ 83 "console=ttyO2,115200n8\0" \ 84 "mpurate=600\0" \ 85 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 86 "tv_mode=omapfb.mode=tv:ntsc\0" \ 87 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 88 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 89 "extra_options= \0" \ 90 "mmcdev=0\0" \ 91 "mmcroot=/dev/mmcblk0p2 rw\0" \ 92 "mmcrootfstype=ext3 rootwait\0" \ 93 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 94 "nandrootfstype=ubifs\0" \ 95 "mmcargs=setenv bootargs console=${console} " \ 96 "mpurate=${mpurate} " \ 97 "${video_mode} " \ 98 "root=${mmcroot} " \ 99 "rootfstype=${mmcrootfstype} " \ 100 "${extra_options}\0" \ 101 "nandargs=setenv bootargs console=${console} " \ 102 "mpurate=${mpurate} " \ 103 "${video_mode} " \ 104 "${network_setting} " \ 105 "root=${nandroot} " \ 106 "rootfstype=${nandrootfstype} "\ 107 "${extra_options}\0" \ 108 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 109 "bootscript=echo Running bootscript from mmc ...; " \ 110 "source ${loadaddr}\0" \ 111 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 112 "mmcboot=echo Booting from mmc ...; " \ 113 "run mmcargs; " \ 114 "bootm ${loadaddr}\0" \ 115 "nandboot=echo Booting from nand ...; " \ 116 "run nandargs; " \ 117 "nand read ${loadaddr} 280000 400000; " \ 118 "bootm ${loadaddr}\0" \ 119 120 #define CONFIG_BOOTCOMMAND \ 121 "if mmc rescan ${mmcdev}; then " \ 122 "if run loadbootscript; then " \ 123 "run bootscript; " \ 124 "else " \ 125 "if run loaduimage; then " \ 126 "run mmcboot; " \ 127 "else run nandboot; " \ 128 "fi; " \ 129 "fi; " \ 130 "else run nandboot; fi" 131 132 /* 133 * Miscellaneous configurable options 134 */ 135 136 /* turn on command-line edit/hist/auto */ 137 138 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 139 /* defaults */ 140 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 141 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 142 143 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 144 /* load address */ 145 146 /* 147 * OMAP3 has 12 GP timers, they can be driven by the system clock 148 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 149 * This rate is divided by a local divisor. 150 */ 151 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 152 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 153 154 /* 155 * Physical Memory Map 156 */ 157 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 158 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 159 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 160 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 161 162 /* 163 * FLASH and environment organization 164 */ 165 166 /* **** PISMO SUPPORT *** */ 167 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 168 #define CONFIG_SYS_FLASH_BASE NAND_BASE 169 170 /* Monitor at start of flash */ 171 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 172 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 173 174 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 175 176 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 177 #define CONFIG_ENV_OFFSET 0x260000 178 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 179 180 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 181 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 182 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 183 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 184 CONFIG_SYS_INIT_RAM_SIZE - \ 185 GENERATED_GBL_DATA_SIZE) 186 187 /* 188 * USB 189 * 190 * Currently only EHCI is enabled, the MUSB OTG controller 191 * is not enabled. 192 */ 193 194 /* USB EHCI */ 195 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 196 197 /* Defines for SPL */ 198 199 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 200 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 201 202 #define CONFIG_SPL_NAND_BASE 203 #define CONFIG_SPL_NAND_DRIVERS 204 #define CONFIG_SPL_NAND_ECC 205 206 /* NAND boot config */ 207 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 208 #define CONFIG_SYS_NAND_PAGE_COUNT 64 209 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 210 #define CONFIG_SYS_NAND_OOBSIZE 64 211 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 212 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 213 /* 214 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 215 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 216 */ 217 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 218 10, 11, 12, 13 } 219 #define CONFIG_SYS_NAND_ECCSIZE 512 220 #define CONFIG_SYS_NAND_ECCBYTES 3 221 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 222 223 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 224 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 225 226 #define CONFIG_SPL_TEXT_BASE 0x40200800 227 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 228 CONFIG_SPL_TEXT_BASE) 229 230 /* 231 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 232 * older x-loader implementations. And move the BSS area so that it 233 * doesn't overlap with TEXT_BASE. 234 */ 235 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 236 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 237 238 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 239 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 240 241 #endif /* __CONFIG_H */ 242