1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 20 #include <asm/arch/cpu.h> /* get chip and board defs */ 21 #include <asm/arch/omap.h> 22 23 /* Clock Defines */ 24 #define V_OSCK 26000000 /* Clock output from T2 */ 25 #define V_SCLK (V_OSCK >> 1) 26 27 #define CONFIG_MISC_INIT_R 28 29 #define CONFIG_CMDLINE_TAG 30 #define CONFIG_SETUP_MEMORY_TAGS 31 #define CONFIG_INITRD_TAG 32 #define CONFIG_REVISION_TAG 33 34 /* 35 * Size of malloc() pool 36 */ 37 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 38 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 39 40 /* 41 * Hardware drivers 42 */ 43 44 /* 45 * NS16550 Configuration 46 */ 47 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 48 49 #define CONFIG_SYS_NS16550_SERIAL 50 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 51 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 52 53 /* 54 * select serial console configuration 55 */ 56 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 57 58 /* allow to overwrite serial and ethaddr */ 59 #define CONFIG_ENV_OVERWRITE 60 61 /* commands to include */ 62 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 63 64 #define CONFIG_SYS_I2C 65 #define CONFIG_I2C_MULTI_BUS 66 67 /* 68 * TWL4030 69 */ 70 #define CONFIG_TWL4030_LED 71 72 /* 73 * Board NAND Info. 74 */ 75 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 76 /* to access nand */ 77 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 78 /* to access nand at */ 79 /* CS0 */ 80 81 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 82 /* devices */ 83 /* Environment information */ 84 85 #define CONFIG_EXTRA_ENV_SETTINGS \ 86 "loadaddr=0x82000000\0" \ 87 "console=ttyO2,115200n8\0" \ 88 "mpurate=600\0" \ 89 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 90 "tv_mode=omapfb.mode=tv:ntsc\0" \ 91 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 92 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 93 "extra_options= \0" \ 94 "mmcdev=0\0" \ 95 "mmcroot=/dev/mmcblk0p2 rw\0" \ 96 "mmcrootfstype=ext3 rootwait\0" \ 97 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 98 "nandrootfstype=ubifs\0" \ 99 "mmcargs=setenv bootargs console=${console} " \ 100 "mpurate=${mpurate} " \ 101 "${video_mode} " \ 102 "root=${mmcroot} " \ 103 "rootfstype=${mmcrootfstype} " \ 104 "${extra_options}\0" \ 105 "nandargs=setenv bootargs console=${console} " \ 106 "mpurate=${mpurate} " \ 107 "${video_mode} " \ 108 "${network_setting} " \ 109 "root=${nandroot} " \ 110 "rootfstype=${nandrootfstype} "\ 111 "${extra_options}\0" \ 112 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 113 "bootscript=echo Running bootscript from mmc ...; " \ 114 "source ${loadaddr}\0" \ 115 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 116 "mmcboot=echo Booting from mmc ...; " \ 117 "run mmcargs; " \ 118 "bootm ${loadaddr}\0" \ 119 "nandboot=echo Booting from nand ...; " \ 120 "run nandargs; " \ 121 "nand read ${loadaddr} 280000 400000; " \ 122 "bootm ${loadaddr}\0" \ 123 124 #define CONFIG_BOOTCOMMAND \ 125 "if mmc rescan ${mmcdev}; then " \ 126 "if run loadbootscript; then " \ 127 "run bootscript; " \ 128 "else " \ 129 "if run loaduimage; then " \ 130 "run mmcboot; " \ 131 "else run nandboot; " \ 132 "fi; " \ 133 "fi; " \ 134 "else run nandboot; fi" 135 136 /* 137 * Miscellaneous configurable options 138 */ 139 140 /* turn on command-line edit/hist/auto */ 141 142 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 143 /* defaults */ 144 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 145 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 146 147 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 148 /* load address */ 149 150 /* 151 * OMAP3 has 12 GP timers, they can be driven by the system clock 152 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 153 * This rate is divided by a local divisor. 154 */ 155 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 156 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 157 158 /* 159 * Physical Memory Map 160 */ 161 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 162 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 163 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 164 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 165 166 /* 167 * FLASH and environment organization 168 */ 169 170 /* **** PISMO SUPPORT *** */ 171 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 172 #define CONFIG_SYS_FLASH_BASE NAND_BASE 173 174 /* Monitor at start of flash */ 175 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 176 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 177 178 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 179 180 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 181 #define CONFIG_ENV_OFFSET 0x260000 182 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 183 184 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 185 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 186 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 187 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 188 CONFIG_SYS_INIT_RAM_SIZE - \ 189 GENERATED_GBL_DATA_SIZE) 190 191 /* 192 * USB 193 * 194 * Currently only EHCI is enabled, the MUSB OTG controller 195 * is not enabled. 196 */ 197 198 /* USB EHCI */ 199 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 200 201 /* Defines for SPL */ 202 203 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 204 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 205 206 #define CONFIG_SPL_NAND_BASE 207 #define CONFIG_SPL_NAND_DRIVERS 208 #define CONFIG_SPL_NAND_ECC 209 210 /* NAND boot config */ 211 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 212 #define CONFIG_SYS_NAND_PAGE_COUNT 64 213 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 214 #define CONFIG_SYS_NAND_OOBSIZE 64 215 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 216 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 217 /* 218 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 219 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 220 */ 221 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 222 10, 11, 12, 13 } 223 #define CONFIG_SYS_NAND_ECCSIZE 512 224 #define CONFIG_SYS_NAND_ECCBYTES 3 225 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 226 227 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 228 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 229 230 #define CONFIG_SPL_TEXT_BASE 0x40200800 231 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 232 CONFIG_SPL_TEXT_BASE) 233 234 /* 235 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 236 * older x-loader implementations. And move the BSS area so that it 237 * doesn't overlap with TEXT_BASE. 238 */ 239 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 240 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 241 242 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 243 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 244 245 #endif /* __CONFIG_H */ 246