1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP /* in a TI OMAP core */ 20 21 #define CONFIG_OMAP_GPIO 22 #define CONFIG_OMAP_COMMON 23 /* Common ARM Erratas */ 24 #define CONFIG_ARM_ERRATA_454179 25 #define CONFIG_ARM_ERRATA_430973 26 #define CONFIG_ARM_ERRATA_621766 27 28 #define MACH_TYPE_OMAP3_TAO3530 2836 29 30 #define CONFIG_SDRC /* Has an SDRC controller */ 31 32 #include <asm/arch/cpu.h> /* get chip and board defs */ 33 #include <asm/arch/omap.h> 34 35 /* 36 * Display CPU and Board information 37 */ 38 #define CONFIG_DISPLAY_CPUINFO 39 #define CONFIG_DISPLAY_BOARDINFO 40 41 /* Clock Defines */ 42 #define V_OSCK 26000000 /* Clock output from T2 */ 43 #define V_SCLK (V_OSCK >> 1) 44 45 #define CONFIG_MISC_INIT_R 46 47 #define CONFIG_CMDLINE_TAG 48 #define CONFIG_SETUP_MEMORY_TAGS 49 #define CONFIG_INITRD_TAG 50 #define CONFIG_REVISION_TAG 51 52 /* 53 * Size of malloc() pool 54 */ 55 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 56 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 57 58 /* 59 * Hardware drivers 60 */ 61 62 /* 63 * NS16550 Configuration 64 */ 65 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 66 67 #define CONFIG_SYS_NS16550_SERIAL 68 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 69 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 70 71 /* 72 * select serial console configuration 73 */ 74 #define CONFIG_CONS_INDEX 3 75 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 76 77 /* allow to overwrite serial and ethaddr */ 78 #define CONFIG_ENV_OVERWRITE 79 #define CONFIG_BAUDRATE 115200 80 #define CONFIG_GENERIC_MMC 81 #define CONFIG_MMC 82 #define CONFIG_OMAP_HSMMC 83 #define CONFIG_DOS_PARTITION 84 85 /* GPIO banks */ 86 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ 87 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ 88 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ 89 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ 90 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ 91 92 /* commands to include */ 93 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 94 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 95 #define MTDIDS_DEFAULT "nand0=nand" 96 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 97 "1920k(u-boot),128k(u-boot-env),"\ 98 "4m(kernel),-(fs)" 99 100 #define CONFIG_CMD_NAND /* NAND support */ 101 102 #define CONFIG_SYS_NO_FLASH 103 #define CONFIG_SYS_I2C 104 #define CONFIG_SYS_I2C_OMAP34XX 105 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 106 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 107 #define CONFIG_I2C_MULTI_BUS 108 109 /* 110 * TWL4030 111 */ 112 #define CONFIG_TWL4030_POWER 113 #define CONFIG_TWL4030_LED 114 115 /* 116 * Board NAND Info. 117 */ 118 #define CONFIG_NAND_OMAP_GPMC 119 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 120 /* to access nand */ 121 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 122 /* to access nand at */ 123 /* CS0 */ 124 125 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 126 /* devices */ 127 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 128 /* Environment information */ 129 130 #define CONFIG_EXTRA_ENV_SETTINGS \ 131 "loadaddr=0x82000000\0" \ 132 "console=ttyO2,115200n8\0" \ 133 "mpurate=600\0" \ 134 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 135 "tv_mode=omapfb.mode=tv:ntsc\0" \ 136 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 137 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 138 "extra_options= \0" \ 139 "mmcdev=0\0" \ 140 "mmcroot=/dev/mmcblk0p2 rw\0" \ 141 "mmcrootfstype=ext3 rootwait\0" \ 142 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 143 "nandrootfstype=ubifs\0" \ 144 "mmcargs=setenv bootargs console=${console} " \ 145 "mpurate=${mpurate} " \ 146 "${video_mode} " \ 147 "root=${mmcroot} " \ 148 "rootfstype=${mmcrootfstype} " \ 149 "${extra_options}\0" \ 150 "nandargs=setenv bootargs console=${console} " \ 151 "mpurate=${mpurate} " \ 152 "${video_mode} " \ 153 "${network_setting} " \ 154 "root=${nandroot} " \ 155 "rootfstype=${nandrootfstype} "\ 156 "${extra_options}\0" \ 157 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 158 "bootscript=echo Running bootscript from mmc ...; " \ 159 "source ${loadaddr}\0" \ 160 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 161 "mmcboot=echo Booting from mmc ...; " \ 162 "run mmcargs; " \ 163 "bootm ${loadaddr}\0" \ 164 "nandboot=echo Booting from nand ...; " \ 165 "run nandargs; " \ 166 "nand read ${loadaddr} 280000 400000; " \ 167 "bootm ${loadaddr}\0" \ 168 169 #define CONFIG_BOOTCOMMAND \ 170 "if mmc rescan ${mmcdev}; then " \ 171 "if run loadbootscript; then " \ 172 "run bootscript; " \ 173 "else " \ 174 "if run loaduimage; then " \ 175 "run mmcboot; " \ 176 "else run nandboot; " \ 177 "fi; " \ 178 "fi; " \ 179 "else run nandboot; fi" 180 181 /* 182 * Miscellaneous configurable options 183 */ 184 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 185 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 186 187 /* turn on command-line edit/hist/auto */ 188 #define CONFIG_CMDLINE_EDITING 189 #define CONFIG_COMMAND_HISTORY 190 #define CONFIG_AUTO_COMPLETE 191 192 /* Print Buffer Size */ 193 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 194 sizeof(CONFIG_SYS_PROMPT) + 16) 195 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 196 /* Boot Argument Buffer Size */ 197 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 198 199 #define CONFIG_SYS_ALT_MEMTEST 1 200 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 201 /* defaults */ 202 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 203 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 204 205 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 206 /* load address */ 207 #define CONFIG_SYS_TEXT_BASE 0x80008000 208 209 /* 210 * OMAP3 has 12 GP timers, they can be driven by the system clock 211 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 212 * This rate is divided by a local divisor. 213 */ 214 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 215 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 216 217 /* 218 * Stack sizes 219 * 220 * The stack sizes are set up in start.S using the settings below 221 */ 222 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 223 224 /* 225 * Physical Memory Map 226 */ 227 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 228 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 229 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 230 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 231 232 /* 233 * FLASH and environment organization 234 */ 235 236 /* **** PISMO SUPPORT *** */ 237 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 238 #define CONFIG_SYS_FLASH_BASE NAND_BASE 239 240 /* Monitor at start of flash */ 241 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 242 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 243 244 #define CONFIG_ENV_IS_IN_NAND 1 245 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 246 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 247 248 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 249 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 250 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 251 252 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 253 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 254 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 255 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 256 CONFIG_SYS_INIT_RAM_SIZE - \ 257 GENERATED_GBL_DATA_SIZE) 258 259 #define CONFIG_OMAP3_SPI 260 261 /* 262 * USB 263 * 264 * Currently only EHCI is enabled, the MUSB OTG controller 265 * is not enabled. 266 */ 267 268 /* USB EHCI */ 269 #define CONFIG_USB_EHCI 270 #define CONFIG_USB_EHCI_OMAP 271 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 272 273 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 274 #define CONFIG_USB_HOST_ETHER 275 #define CONFIG_USB_ETHER_SMSC95XX 276 277 #define CONFIG_USB_ETHER 278 #define CONFIG_USB_ETHER_RNDIS 279 #define CONGIG_CMD_STORAGE 280 281 /* Defines for SPL */ 282 #define CONFIG_SPL_FRAMEWORK 283 #define CONFIG_SPL_NAND_SIMPLE 284 285 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 286 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 287 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 288 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 289 290 #define CONFIG_SPL_BOARD_INIT 291 #define CONFIG_SPL_NAND_BASE 292 #define CONFIG_SPL_NAND_DRIVERS 293 #define CONFIG_SPL_NAND_ECC 294 #define CONFIG_SPL_OMAP3_ID_NAND 295 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 296 297 /* NAND boot config */ 298 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 299 #define CONFIG_SYS_NAND_PAGE_COUNT 64 300 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 301 #define CONFIG_SYS_NAND_OOBSIZE 64 302 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 303 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 304 /* 305 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 306 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 307 */ 308 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 309 10, 11, 12, 13 } 310 #define CONFIG_SYS_NAND_ECCSIZE 512 311 #define CONFIG_SYS_NAND_ECCBYTES 3 312 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 313 314 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 315 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 316 317 #define CONFIG_SPL_TEXT_BASE 0x40200800 318 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 319 CONFIG_SPL_TEXT_BASE) 320 321 /* 322 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 323 * older x-loader implementations. And move the BSS area so that it 324 * doesn't overlap with TEXT_BASE. 325 */ 326 #define CONFIG_SYS_TEXT_BASE 0x80008000 327 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 328 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 329 330 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 331 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 332 333 #endif /* __CONFIG_H */ 334