1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP /* in a TI OMAP core */ 20 21 #define CONFIG_OMAP_GPIO 22 /* Common ARM Erratas */ 23 #define CONFIG_ARM_ERRATA_454179 24 #define CONFIG_ARM_ERRATA_430973 25 #define CONFIG_ARM_ERRATA_621766 26 27 #define MACH_TYPE_OMAP3_TAO3530 2836 28 29 #define CONFIG_SDRC /* Has an SDRC controller */ 30 31 #include <asm/arch/cpu.h> /* get chip and board defs */ 32 #include <asm/arch/omap.h> 33 34 /* Clock Defines */ 35 #define V_OSCK 26000000 /* Clock output from T2 */ 36 #define V_SCLK (V_OSCK >> 1) 37 38 #define CONFIG_MISC_INIT_R 39 40 #define CONFIG_CMDLINE_TAG 41 #define CONFIG_SETUP_MEMORY_TAGS 42 #define CONFIG_INITRD_TAG 43 #define CONFIG_REVISION_TAG 44 45 /* 46 * Size of malloc() pool 47 */ 48 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 49 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 50 51 /* 52 * Hardware drivers 53 */ 54 55 /* 56 * NS16550 Configuration 57 */ 58 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 59 60 #define CONFIG_SYS_NS16550_SERIAL 61 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 62 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 63 64 /* 65 * select serial console configuration 66 */ 67 #define CONFIG_CONS_INDEX 3 68 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 69 70 /* allow to overwrite serial and ethaddr */ 71 #define CONFIG_ENV_OVERWRITE 72 #define CONFIG_BAUDRATE 115200 73 #define CONFIG_GENERIC_MMC 74 #define CONFIG_OMAP_HSMMC 75 #define CONFIG_DOS_PARTITION 76 77 /* GPIO banks */ 78 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ 79 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ 80 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ 81 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ 82 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ 83 84 /* commands to include */ 85 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 86 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 87 #define MTDIDS_DEFAULT "nand0=nand" 88 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 89 "1920k(u-boot),128k(u-boot-env),"\ 90 "4m(kernel),-(fs)" 91 92 #define CONFIG_CMD_NAND /* NAND support */ 93 94 #define CONFIG_SYS_NO_FLASH 95 #define CONFIG_SYS_I2C 96 #define CONFIG_SYS_I2C_OMAP34XX 97 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 98 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 99 #define CONFIG_I2C_MULTI_BUS 100 101 /* 102 * TWL4030 103 */ 104 #define CONFIG_TWL4030_POWER 105 #define CONFIG_TWL4030_LED 106 107 /* 108 * Board NAND Info. 109 */ 110 #define CONFIG_NAND_OMAP_GPMC 111 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 112 /* to access nand */ 113 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 114 /* to access nand at */ 115 /* CS0 */ 116 117 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 118 /* devices */ 119 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 120 /* Environment information */ 121 122 #define CONFIG_EXTRA_ENV_SETTINGS \ 123 "loadaddr=0x82000000\0" \ 124 "console=ttyO2,115200n8\0" \ 125 "mpurate=600\0" \ 126 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 127 "tv_mode=omapfb.mode=tv:ntsc\0" \ 128 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 129 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 130 "extra_options= \0" \ 131 "mmcdev=0\0" \ 132 "mmcroot=/dev/mmcblk0p2 rw\0" \ 133 "mmcrootfstype=ext3 rootwait\0" \ 134 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 135 "nandrootfstype=ubifs\0" \ 136 "mmcargs=setenv bootargs console=${console} " \ 137 "mpurate=${mpurate} " \ 138 "${video_mode} " \ 139 "root=${mmcroot} " \ 140 "rootfstype=${mmcrootfstype} " \ 141 "${extra_options}\0" \ 142 "nandargs=setenv bootargs console=${console} " \ 143 "mpurate=${mpurate} " \ 144 "${video_mode} " \ 145 "${network_setting} " \ 146 "root=${nandroot} " \ 147 "rootfstype=${nandrootfstype} "\ 148 "${extra_options}\0" \ 149 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 150 "bootscript=echo Running bootscript from mmc ...; " \ 151 "source ${loadaddr}\0" \ 152 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 153 "mmcboot=echo Booting from mmc ...; " \ 154 "run mmcargs; " \ 155 "bootm ${loadaddr}\0" \ 156 "nandboot=echo Booting from nand ...; " \ 157 "run nandargs; " \ 158 "nand read ${loadaddr} 280000 400000; " \ 159 "bootm ${loadaddr}\0" \ 160 161 #define CONFIG_BOOTCOMMAND \ 162 "if mmc rescan ${mmcdev}; then " \ 163 "if run loadbootscript; then " \ 164 "run bootscript; " \ 165 "else " \ 166 "if run loaduimage; then " \ 167 "run mmcboot; " \ 168 "else run nandboot; " \ 169 "fi; " \ 170 "fi; " \ 171 "else run nandboot; fi" 172 173 /* 174 * Miscellaneous configurable options 175 */ 176 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 177 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 178 179 /* turn on command-line edit/hist/auto */ 180 #define CONFIG_CMDLINE_EDITING 181 #define CONFIG_COMMAND_HISTORY 182 #define CONFIG_AUTO_COMPLETE 183 184 /* Print Buffer Size */ 185 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 186 sizeof(CONFIG_SYS_PROMPT) + 16) 187 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 188 /* Boot Argument Buffer Size */ 189 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 190 191 #define CONFIG_SYS_ALT_MEMTEST 1 192 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 193 /* defaults */ 194 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 195 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 196 197 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 198 /* load address */ 199 #define CONFIG_SYS_TEXT_BASE 0x80008000 200 201 /* 202 * OMAP3 has 12 GP timers, they can be driven by the system clock 203 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 204 * This rate is divided by a local divisor. 205 */ 206 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 207 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 208 209 /* 210 * Stack sizes 211 * 212 * The stack sizes are set up in start.S using the settings below 213 */ 214 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 215 216 /* 217 * Physical Memory Map 218 */ 219 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 220 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 221 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 222 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 223 224 /* 225 * FLASH and environment organization 226 */ 227 228 /* **** PISMO SUPPORT *** */ 229 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 230 #define CONFIG_SYS_FLASH_BASE NAND_BASE 231 232 /* Monitor at start of flash */ 233 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 234 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 235 236 #define CONFIG_ENV_IS_IN_NAND 1 237 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 238 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 239 240 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 241 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 242 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 243 244 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 245 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 246 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 247 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 248 CONFIG_SYS_INIT_RAM_SIZE - \ 249 GENERATED_GBL_DATA_SIZE) 250 251 #define CONFIG_OMAP3_SPI 252 253 /* 254 * USB 255 * 256 * Currently only EHCI is enabled, the MUSB OTG controller 257 * is not enabled. 258 */ 259 260 /* USB EHCI */ 261 #define CONFIG_USB_EHCI 262 #define CONFIG_USB_EHCI_OMAP 263 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 264 265 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 266 #define CONFIG_USB_HOST_ETHER 267 #define CONFIG_USB_ETHER_SMSC95XX 268 269 #define CONFIG_USB_ETHER 270 #define CONFIG_USB_ETHER_RNDIS 271 #define CONGIG_CMD_STORAGE 272 273 /* Defines for SPL */ 274 #define CONFIG_SPL_FRAMEWORK 275 #define CONFIG_SPL_NAND_SIMPLE 276 277 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 278 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 279 280 #define CONFIG_SPL_BOARD_INIT 281 #define CONFIG_SPL_NAND_BASE 282 #define CONFIG_SPL_NAND_DRIVERS 283 #define CONFIG_SPL_NAND_ECC 284 #define CONFIG_SPL_OMAP3_ID_NAND 285 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 286 287 /* NAND boot config */ 288 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 289 #define CONFIG_SYS_NAND_PAGE_COUNT 64 290 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 291 #define CONFIG_SYS_NAND_OOBSIZE 64 292 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 293 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 294 /* 295 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 296 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 297 */ 298 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 299 10, 11, 12, 13 } 300 #define CONFIG_SYS_NAND_ECCSIZE 512 301 #define CONFIG_SYS_NAND_ECCBYTES 3 302 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 303 304 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 305 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 306 307 #define CONFIG_SPL_TEXT_BASE 0x40200800 308 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 309 CONFIG_SPL_TEXT_BASE) 310 311 /* 312 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 313 * older x-loader implementations. And move the BSS area so that it 314 * doesn't overlap with TEXT_BASE. 315 */ 316 #define CONFIG_SYS_TEXT_BASE 0x80008000 317 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 318 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 319 320 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 321 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 322 323 #endif /* __CONFIG_H */ 324