1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP /* in a TI OMAP core */ 20 21 #define CONFIG_OMAP_GPIO 22 /* Common ARM Erratas */ 23 #define CONFIG_ARM_ERRATA_454179 24 #define CONFIG_ARM_ERRATA_430973 25 #define CONFIG_ARM_ERRATA_621766 26 27 #define CONFIG_SDRC /* Has an SDRC controller */ 28 29 #include <asm/arch/cpu.h> /* get chip and board defs */ 30 #include <asm/arch/omap.h> 31 32 /* Clock Defines */ 33 #define V_OSCK 26000000 /* Clock output from T2 */ 34 #define V_SCLK (V_OSCK >> 1) 35 36 #define CONFIG_MISC_INIT_R 37 38 #define CONFIG_CMDLINE_TAG 39 #define CONFIG_SETUP_MEMORY_TAGS 40 #define CONFIG_INITRD_TAG 41 #define CONFIG_REVISION_TAG 42 43 /* 44 * Size of malloc() pool 45 */ 46 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 47 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 48 49 /* 50 * Hardware drivers 51 */ 52 53 /* 54 * NS16550 Configuration 55 */ 56 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 57 58 #define CONFIG_SYS_NS16550_SERIAL 59 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 60 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 61 62 /* 63 * select serial console configuration 64 */ 65 #define CONFIG_CONS_INDEX 3 66 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 67 68 /* allow to overwrite serial and ethaddr */ 69 #define CONFIG_ENV_OVERWRITE 70 #define CONFIG_BAUDRATE 115200 71 72 /* GPIO banks */ 73 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ 74 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ 75 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ 76 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ 77 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ 78 79 /* commands to include */ 80 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 81 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 82 #define MTDIDS_DEFAULT "nand0=nand" 83 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 84 "1920k(u-boot),128k(u-boot-env),"\ 85 "4m(kernel),-(fs)" 86 87 #define CONFIG_CMD_NAND /* NAND support */ 88 89 #define CONFIG_SYS_NO_FLASH 90 #define CONFIG_SYS_I2C 91 #define CONFIG_SYS_I2C_OMAP34XX 92 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 93 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 94 #define CONFIG_I2C_MULTI_BUS 95 96 /* 97 * TWL4030 98 */ 99 #define CONFIG_TWL4030_POWER 100 #define CONFIG_TWL4030_LED 101 102 /* 103 * Board NAND Info. 104 */ 105 #define CONFIG_NAND_OMAP_GPMC 106 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 107 /* to access nand */ 108 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 109 /* to access nand at */ 110 /* CS0 */ 111 112 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 113 /* devices */ 114 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 115 /* Environment information */ 116 117 #define CONFIG_EXTRA_ENV_SETTINGS \ 118 "loadaddr=0x82000000\0" \ 119 "console=ttyO2,115200n8\0" \ 120 "mpurate=600\0" \ 121 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 122 "tv_mode=omapfb.mode=tv:ntsc\0" \ 123 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 124 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 125 "extra_options= \0" \ 126 "mmcdev=0\0" \ 127 "mmcroot=/dev/mmcblk0p2 rw\0" \ 128 "mmcrootfstype=ext3 rootwait\0" \ 129 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 130 "nandrootfstype=ubifs\0" \ 131 "mmcargs=setenv bootargs console=${console} " \ 132 "mpurate=${mpurate} " \ 133 "${video_mode} " \ 134 "root=${mmcroot} " \ 135 "rootfstype=${mmcrootfstype} " \ 136 "${extra_options}\0" \ 137 "nandargs=setenv bootargs console=${console} " \ 138 "mpurate=${mpurate} " \ 139 "${video_mode} " \ 140 "${network_setting} " \ 141 "root=${nandroot} " \ 142 "rootfstype=${nandrootfstype} "\ 143 "${extra_options}\0" \ 144 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 145 "bootscript=echo Running bootscript from mmc ...; " \ 146 "source ${loadaddr}\0" \ 147 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 148 "mmcboot=echo Booting from mmc ...; " \ 149 "run mmcargs; " \ 150 "bootm ${loadaddr}\0" \ 151 "nandboot=echo Booting from nand ...; " \ 152 "run nandargs; " \ 153 "nand read ${loadaddr} 280000 400000; " \ 154 "bootm ${loadaddr}\0" \ 155 156 #define CONFIG_BOOTCOMMAND \ 157 "if mmc rescan ${mmcdev}; then " \ 158 "if run loadbootscript; then " \ 159 "run bootscript; " \ 160 "else " \ 161 "if run loaduimage; then " \ 162 "run mmcboot; " \ 163 "else run nandboot; " \ 164 "fi; " \ 165 "fi; " \ 166 "else run nandboot; fi" 167 168 /* 169 * Miscellaneous configurable options 170 */ 171 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 172 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 173 174 /* turn on command-line edit/hist/auto */ 175 #define CONFIG_CMDLINE_EDITING 176 #define CONFIG_COMMAND_HISTORY 177 #define CONFIG_AUTO_COMPLETE 178 179 /* Print Buffer Size */ 180 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 181 sizeof(CONFIG_SYS_PROMPT) + 16) 182 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 183 /* Boot Argument Buffer Size */ 184 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 185 186 #define CONFIG_SYS_ALT_MEMTEST 1 187 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 188 /* defaults */ 189 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 190 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 191 192 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 193 /* load address */ 194 #define CONFIG_SYS_TEXT_BASE 0x80008000 195 196 /* 197 * OMAP3 has 12 GP timers, they can be driven by the system clock 198 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 199 * This rate is divided by a local divisor. 200 */ 201 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 202 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 203 204 /* 205 * Stack sizes 206 * 207 * The stack sizes are set up in start.S using the settings below 208 */ 209 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 210 211 /* 212 * Physical Memory Map 213 */ 214 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 215 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 216 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 217 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 218 219 /* 220 * FLASH and environment organization 221 */ 222 223 /* **** PISMO SUPPORT *** */ 224 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 225 #define CONFIG_SYS_FLASH_BASE NAND_BASE 226 227 /* Monitor at start of flash */ 228 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 229 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 230 231 #define CONFIG_ENV_IS_IN_NAND 1 232 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 233 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 234 235 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 236 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 237 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 238 239 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 240 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 241 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 242 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 243 CONFIG_SYS_INIT_RAM_SIZE - \ 244 GENERATED_GBL_DATA_SIZE) 245 246 #define CONFIG_OMAP3_SPI 247 248 /* 249 * USB 250 * 251 * Currently only EHCI is enabled, the MUSB OTG controller 252 * is not enabled. 253 */ 254 255 /* USB EHCI */ 256 #define CONFIG_USB_EHCI 257 #define CONFIG_USB_EHCI_OMAP 258 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 259 260 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 261 #define CONFIG_USB_HOST_ETHER 262 #define CONFIG_USB_ETHER_SMSC95XX 263 264 #define CONFIG_USB_ETHER 265 #define CONFIG_USB_ETHER_RNDIS 266 #define CONGIG_CMD_STORAGE 267 268 /* Defines for SPL */ 269 #define CONFIG_SPL_FRAMEWORK 270 #define CONFIG_SPL_NAND_SIMPLE 271 272 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 273 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 274 275 #define CONFIG_SPL_BOARD_INIT 276 #define CONFIG_SPL_NAND_BASE 277 #define CONFIG_SPL_NAND_DRIVERS 278 #define CONFIG_SPL_NAND_ECC 279 #define CONFIG_SPL_OMAP3_ID_NAND 280 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 281 282 /* NAND boot config */ 283 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 284 #define CONFIG_SYS_NAND_PAGE_COUNT 64 285 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 286 #define CONFIG_SYS_NAND_OOBSIZE 64 287 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 288 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 289 /* 290 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 291 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 292 */ 293 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 294 10, 11, 12, 13 } 295 #define CONFIG_SYS_NAND_ECCSIZE 512 296 #define CONFIG_SYS_NAND_ECCBYTES 3 297 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 298 299 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 300 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 301 302 #define CONFIG_SPL_TEXT_BASE 0x40200800 303 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 304 CONFIG_SPL_TEXT_BASE) 305 306 /* 307 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 308 * older x-loader implementations. And move the BSS area so that it 309 * doesn't overlap with TEXT_BASE. 310 */ 311 #define CONFIG_SYS_TEXT_BASE 0x80008000 312 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 313 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 314 315 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 316 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 317 318 #endif /* __CONFIG_H */ 319