1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP /* in a TI OMAP core */ 20 21 #define CONFIG_OMAP_GPIO 22 /* Common ARM Erratas */ 23 #define CONFIG_ARM_ERRATA_454179 24 #define CONFIG_ARM_ERRATA_430973 25 #define CONFIG_ARM_ERRATA_621766 26 27 #define MACH_TYPE_OMAP3_TAO3530 2836 28 29 #define CONFIG_SDRC /* Has an SDRC controller */ 30 31 #include <asm/arch/cpu.h> /* get chip and board defs */ 32 #include <asm/arch/omap.h> 33 34 /* Clock Defines */ 35 #define V_OSCK 26000000 /* Clock output from T2 */ 36 #define V_SCLK (V_OSCK >> 1) 37 38 #define CONFIG_MISC_INIT_R 39 40 #define CONFIG_CMDLINE_TAG 41 #define CONFIG_SETUP_MEMORY_TAGS 42 #define CONFIG_INITRD_TAG 43 #define CONFIG_REVISION_TAG 44 45 /* 46 * Size of malloc() pool 47 */ 48 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 49 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 50 51 /* 52 * Hardware drivers 53 */ 54 55 /* 56 * NS16550 Configuration 57 */ 58 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 59 60 #define CONFIG_SYS_NS16550_SERIAL 61 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 62 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 63 64 /* 65 * select serial console configuration 66 */ 67 #define CONFIG_CONS_INDEX 3 68 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 69 70 /* allow to overwrite serial and ethaddr */ 71 #define CONFIG_ENV_OVERWRITE 72 #define CONFIG_BAUDRATE 115200 73 #define CONFIG_GENERIC_MMC 74 #define CONFIG_DOS_PARTITION 75 76 /* GPIO banks */ 77 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ 78 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ 79 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ 80 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ 81 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ 82 83 /* commands to include */ 84 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 85 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 86 #define MTDIDS_DEFAULT "nand0=nand" 87 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 88 "1920k(u-boot),128k(u-boot-env),"\ 89 "4m(kernel),-(fs)" 90 91 #define CONFIG_CMD_NAND /* NAND support */ 92 93 #define CONFIG_SYS_NO_FLASH 94 #define CONFIG_SYS_I2C 95 #define CONFIG_SYS_I2C_OMAP34XX 96 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 97 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 98 #define CONFIG_I2C_MULTI_BUS 99 100 /* 101 * TWL4030 102 */ 103 #define CONFIG_TWL4030_POWER 104 #define CONFIG_TWL4030_LED 105 106 /* 107 * Board NAND Info. 108 */ 109 #define CONFIG_NAND_OMAP_GPMC 110 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 111 /* to access nand */ 112 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 113 /* to access nand at */ 114 /* CS0 */ 115 116 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 117 /* devices */ 118 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 119 /* Environment information */ 120 121 #define CONFIG_EXTRA_ENV_SETTINGS \ 122 "loadaddr=0x82000000\0" \ 123 "console=ttyO2,115200n8\0" \ 124 "mpurate=600\0" \ 125 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 126 "tv_mode=omapfb.mode=tv:ntsc\0" \ 127 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 128 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 129 "extra_options= \0" \ 130 "mmcdev=0\0" \ 131 "mmcroot=/dev/mmcblk0p2 rw\0" \ 132 "mmcrootfstype=ext3 rootwait\0" \ 133 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 134 "nandrootfstype=ubifs\0" \ 135 "mmcargs=setenv bootargs console=${console} " \ 136 "mpurate=${mpurate} " \ 137 "${video_mode} " \ 138 "root=${mmcroot} " \ 139 "rootfstype=${mmcrootfstype} " \ 140 "${extra_options}\0" \ 141 "nandargs=setenv bootargs console=${console} " \ 142 "mpurate=${mpurate} " \ 143 "${video_mode} " \ 144 "${network_setting} " \ 145 "root=${nandroot} " \ 146 "rootfstype=${nandrootfstype} "\ 147 "${extra_options}\0" \ 148 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 149 "bootscript=echo Running bootscript from mmc ...; " \ 150 "source ${loadaddr}\0" \ 151 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 152 "mmcboot=echo Booting from mmc ...; " \ 153 "run mmcargs; " \ 154 "bootm ${loadaddr}\0" \ 155 "nandboot=echo Booting from nand ...; " \ 156 "run nandargs; " \ 157 "nand read ${loadaddr} 280000 400000; " \ 158 "bootm ${loadaddr}\0" \ 159 160 #define CONFIG_BOOTCOMMAND \ 161 "if mmc rescan ${mmcdev}; then " \ 162 "if run loadbootscript; then " \ 163 "run bootscript; " \ 164 "else " \ 165 "if run loaduimage; then " \ 166 "run mmcboot; " \ 167 "else run nandboot; " \ 168 "fi; " \ 169 "fi; " \ 170 "else run nandboot; fi" 171 172 /* 173 * Miscellaneous configurable options 174 */ 175 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 176 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 177 178 /* turn on command-line edit/hist/auto */ 179 #define CONFIG_CMDLINE_EDITING 180 #define CONFIG_COMMAND_HISTORY 181 #define CONFIG_AUTO_COMPLETE 182 183 /* Print Buffer Size */ 184 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 185 sizeof(CONFIG_SYS_PROMPT) + 16) 186 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 187 /* Boot Argument Buffer Size */ 188 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 189 190 #define CONFIG_SYS_ALT_MEMTEST 1 191 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 192 /* defaults */ 193 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 194 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 195 196 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 197 /* load address */ 198 #define CONFIG_SYS_TEXT_BASE 0x80008000 199 200 /* 201 * OMAP3 has 12 GP timers, they can be driven by the system clock 202 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 203 * This rate is divided by a local divisor. 204 */ 205 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 206 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 207 208 /* 209 * Stack sizes 210 * 211 * The stack sizes are set up in start.S using the settings below 212 */ 213 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 214 215 /* 216 * Physical Memory Map 217 */ 218 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 219 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 220 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 221 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 222 223 /* 224 * FLASH and environment organization 225 */ 226 227 /* **** PISMO SUPPORT *** */ 228 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 229 #define CONFIG_SYS_FLASH_BASE NAND_BASE 230 231 /* Monitor at start of flash */ 232 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 233 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 234 235 #define CONFIG_ENV_IS_IN_NAND 1 236 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 237 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 238 239 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 240 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 241 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 242 243 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 244 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 245 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 246 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 247 CONFIG_SYS_INIT_RAM_SIZE - \ 248 GENERATED_GBL_DATA_SIZE) 249 250 #define CONFIG_OMAP3_SPI 251 252 /* 253 * USB 254 * 255 * Currently only EHCI is enabled, the MUSB OTG controller 256 * is not enabled. 257 */ 258 259 /* USB EHCI */ 260 #define CONFIG_USB_EHCI 261 #define CONFIG_USB_EHCI_OMAP 262 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 263 264 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 265 #define CONFIG_USB_HOST_ETHER 266 #define CONFIG_USB_ETHER_SMSC95XX 267 268 #define CONFIG_USB_ETHER 269 #define CONFIG_USB_ETHER_RNDIS 270 #define CONGIG_CMD_STORAGE 271 272 /* Defines for SPL */ 273 #define CONFIG_SPL_FRAMEWORK 274 #define CONFIG_SPL_NAND_SIMPLE 275 276 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 277 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 278 279 #define CONFIG_SPL_BOARD_INIT 280 #define CONFIG_SPL_NAND_BASE 281 #define CONFIG_SPL_NAND_DRIVERS 282 #define CONFIG_SPL_NAND_ECC 283 #define CONFIG_SPL_OMAP3_ID_NAND 284 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 285 286 /* NAND boot config */ 287 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 288 #define CONFIG_SYS_NAND_PAGE_COUNT 64 289 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 290 #define CONFIG_SYS_NAND_OOBSIZE 64 291 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 292 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 293 /* 294 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 295 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 296 */ 297 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 298 10, 11, 12, 13 } 299 #define CONFIG_SYS_NAND_ECCSIZE 512 300 #define CONFIG_SYS_NAND_ECCBYTES 3 301 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 302 303 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 304 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 305 306 #define CONFIG_SPL_TEXT_BASE 0x40200800 307 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 308 CONFIG_SPL_TEXT_BASE) 309 310 /* 311 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 312 * older x-loader implementations. And move the BSS area so that it 313 * doesn't overlap with TEXT_BASE. 314 */ 315 #define CONFIG_SYS_TEXT_BASE 0x80008000 316 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 317 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 318 319 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 320 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 321 322 #endif /* __CONFIG_H */ 323