1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP /* in a TI OMAP core */ 20 21 #define CONFIG_OMAP_GPIO 22 #define CONFIG_OMAP_COMMON 23 #define CONFIG_SYS_GENERIC_BOARD 24 /* Common ARM Erratas */ 25 #define CONFIG_ARM_ERRATA_454179 26 #define CONFIG_ARM_ERRATA_430973 27 #define CONFIG_ARM_ERRATA_621766 28 29 #define MACH_TYPE_OMAP3_TAO3530 2836 30 31 #define CONFIG_SDRC /* Has an SDRC controller */ 32 33 #include <asm/arch/cpu.h> /* get chip and board defs */ 34 #include <asm/arch/omap.h> 35 36 /* 37 * Display CPU and Board information 38 */ 39 #define CONFIG_DISPLAY_CPUINFO 40 #define CONFIG_DISPLAY_BOARDINFO 41 42 /* Clock Defines */ 43 #define V_OSCK 26000000 /* Clock output from T2 */ 44 #define V_SCLK (V_OSCK >> 1) 45 46 #define CONFIG_MISC_INIT_R 47 48 #define CONFIG_OF_LIBFDT 49 50 #define CONFIG_CMDLINE_TAG 51 #define CONFIG_SETUP_MEMORY_TAGS 52 #define CONFIG_INITRD_TAG 53 #define CONFIG_REVISION_TAG 54 55 /* 56 * Size of malloc() pool 57 */ 58 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 59 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 60 61 /* 62 * Hardware drivers 63 */ 64 65 /* 66 * NS16550 Configuration 67 */ 68 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 69 70 #define CONFIG_SYS_NS16550 71 #define CONFIG_SYS_NS16550_SERIAL 72 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 73 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 74 75 /* 76 * select serial console configuration 77 */ 78 #define CONFIG_CONS_INDEX 3 79 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 80 81 /* allow to overwrite serial and ethaddr */ 82 #define CONFIG_ENV_OVERWRITE 83 #define CONFIG_BAUDRATE 115200 84 #define CONFIG_GENERIC_MMC 85 #define CONFIG_MMC 86 #define CONFIG_OMAP_HSMMC 87 #define CONFIG_DOS_PARTITION 88 89 /* GPIO banks */ 90 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ 91 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ 92 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ 93 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ 94 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ 95 96 /* commands to include */ 97 #include <config_cmd_default.h> 98 99 #define CONFIG_CMD_CACHE 100 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 101 #define CONFIG_CMD_FAT /* FAT support */ 102 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 103 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 104 #define MTDIDS_DEFAULT "nand0=nand" 105 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 106 "1920k(u-boot),128k(u-boot-env),"\ 107 "4m(kernel),-(fs)" 108 109 #define CONFIG_CMD_I2C /* I2C serial bus support */ 110 #define CONFIG_CMD_MMC /* MMC support */ 111 #define CONFIG_CMD_NAND /* NAND support */ 112 #define CONFIG_CMD_DHCP 113 #define CONFIG_CMD_PING 114 115 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 116 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 117 #undef CONFIG_CMD_IMI /* iminfo */ 118 #undef CONFIG_CMD_IMLS /* List all found images */ 119 120 #define CONFIG_SYS_NO_FLASH 121 #define CONFIG_SYS_I2C 122 #define CONFIG_SYS_I2C_OMAP34XX 123 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 124 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 125 #define CONFIG_I2C_MULTI_BUS 126 127 /* 128 * TWL4030 129 */ 130 #define CONFIG_TWL4030_POWER 131 #define CONFIG_TWL4030_LED 132 133 /* 134 * Board NAND Info. 135 */ 136 #define CONFIG_SYS_NAND_QUIET_TEST 137 #define CONFIG_NAND_OMAP_GPMC 138 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 139 /* to access nand */ 140 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 141 /* to access nand at */ 142 /* CS0 */ 143 144 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 145 /* devices */ 146 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 147 /* Environment information */ 148 #define CONFIG_BOOTDELAY 3 149 150 #define CONFIG_EXTRA_ENV_SETTINGS \ 151 "loadaddr=0x82000000\0" \ 152 "console=ttyO2,115200n8\0" \ 153 "mpurate=600\0" \ 154 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 155 "tv_mode=omapfb.mode=tv:ntsc\0" \ 156 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 157 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 158 "extra_options= \0" \ 159 "mmcdev=0\0" \ 160 "mmcroot=/dev/mmcblk0p2 rw\0" \ 161 "mmcrootfstype=ext3 rootwait\0" \ 162 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 163 "nandrootfstype=ubifs\0" \ 164 "mmcargs=setenv bootargs console=${console} " \ 165 "mpurate=${mpurate} " \ 166 "${video_mode} " \ 167 "root=${mmcroot} " \ 168 "rootfstype=${mmcrootfstype} " \ 169 "${extra_options}\0" \ 170 "nandargs=setenv bootargs console=${console} " \ 171 "mpurate=${mpurate} " \ 172 "${video_mode} " \ 173 "${network_setting} " \ 174 "root=${nandroot} " \ 175 "rootfstype=${nandrootfstype} "\ 176 "${extra_options}\0" \ 177 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 178 "bootscript=echo Running bootscript from mmc ...; " \ 179 "source ${loadaddr}\0" \ 180 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 181 "mmcboot=echo Booting from mmc ...; " \ 182 "run mmcargs; " \ 183 "bootm ${loadaddr}\0" \ 184 "nandboot=echo Booting from nand ...; " \ 185 "run nandargs; " \ 186 "nand read ${loadaddr} 280000 400000; " \ 187 "bootm ${loadaddr}\0" \ 188 189 #define CONFIG_BOOTCOMMAND \ 190 "if mmc rescan ${mmcdev}; then " \ 191 "if run loadbootscript; then " \ 192 "run bootscript; " \ 193 "else " \ 194 "if run loaduimage; then " \ 195 "run mmcboot; " \ 196 "else run nandboot; " \ 197 "fi; " \ 198 "fi; " \ 199 "else run nandboot; fi" 200 201 /* 202 * Miscellaneous configurable options 203 */ 204 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 205 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 206 #define CONFIG_SYS_PROMPT "TAO-3530 # " 207 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 208 209 /* turn on command-line edit/hist/auto */ 210 #define CONFIG_CMDLINE_EDITING 211 #define CONFIG_COMMAND_HISTORY 212 #define CONFIG_AUTO_COMPLETE 213 214 /* Print Buffer Size */ 215 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 216 sizeof(CONFIG_SYS_PROMPT) + 16) 217 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 218 /* Boot Argument Buffer Size */ 219 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 220 221 #define CONFIG_SYS_ALT_MEMTEST 1 222 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 223 /* defaults */ 224 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 225 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 226 227 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 228 /* load address */ 229 #define CONFIG_SYS_TEXT_BASE 0x80008000 230 231 /* 232 * OMAP3 has 12 GP timers, they can be driven by the system clock 233 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 234 * This rate is divided by a local divisor. 235 */ 236 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 237 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 238 239 /* 240 * Stack sizes 241 * 242 * The stack sizes are set up in start.S using the settings below 243 */ 244 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 245 246 /* 247 * Physical Memory Map 248 */ 249 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 250 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 251 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 252 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 253 254 /* 255 * FLASH and environment organization 256 */ 257 258 /* **** PISMO SUPPORT *** */ 259 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 260 #define CONFIG_SYS_FLASH_BASE NAND_BASE 261 262 /* Monitor at start of flash */ 263 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 264 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 265 266 #define CONFIG_ENV_IS_IN_NAND 1 267 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 268 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 269 270 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 271 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 272 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 273 274 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 275 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 276 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 277 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 278 CONFIG_SYS_INIT_RAM_SIZE - \ 279 GENERATED_GBL_DATA_SIZE) 280 281 #define CONFIG_OMAP3_SPI 282 283 /* 284 * USB 285 * 286 * Currently only EHCI is enabled, the MUSB OTG controller 287 * is not enabled. 288 */ 289 290 /* USB EHCI */ 291 #define CONFIG_CMD_USB 292 #define CONFIG_USB_EHCI 293 #define CONFIG_USB_EHCI_OMAP 294 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 295 296 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 297 #define CONFIG_USB_HOST_ETHER 298 #define CONFIG_USB_ETHER_SMSC95XX 299 300 #define CONFIG_USB_ETHER 301 #define CONFIG_USB_ETHER_RNDIS 302 #define CONFIG_USB_STORAGE 303 #define CONGIG_CMD_STORAGE 304 305 /* Defines for SPL */ 306 #define CONFIG_SPL_FRAMEWORK 307 #define CONFIG_SPL_NAND_SIMPLE 308 309 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 310 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 311 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 312 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 313 314 #define CONFIG_SPL_BOARD_INIT 315 #define CONFIG_SPL_LIBCOMMON_SUPPORT 316 #define CONFIG_SPL_LIBDISK_SUPPORT 317 #define CONFIG_SPL_I2C_SUPPORT 318 #define CONFIG_SPL_LIBGENERIC_SUPPORT 319 #define CONFIG_SPL_MMC_SUPPORT 320 #define CONFIG_SPL_FAT_SUPPORT 321 #define CONFIG_SPL_SERIAL_SUPPORT 322 #define CONFIG_SPL_NAND_SUPPORT 323 #define CONFIG_SPL_NAND_BASE 324 #define CONFIG_SPL_NAND_DRIVERS 325 #define CONFIG_SPL_NAND_ECC 326 #define CONFIG_SPL_GPIO_SUPPORT 327 #define CONFIG_SPL_POWER_SUPPORT 328 #define CONFIG_SPL_OMAP3_ID_NAND 329 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 330 331 /* NAND boot config */ 332 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 333 #define CONFIG_SYS_NAND_PAGE_COUNT 64 334 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 335 #define CONFIG_SYS_NAND_OOBSIZE 64 336 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 337 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 338 /* 339 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 340 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 341 */ 342 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 343 10, 11, 12, 13 } 344 #define CONFIG_SYS_NAND_ECCSIZE 512 345 #define CONFIG_SYS_NAND_ECCBYTES 3 346 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 347 348 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 349 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 350 351 #define CONFIG_SPL_TEXT_BASE 0x40200800 352 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 353 354 /* 355 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 356 * older x-loader implementations. And move the BSS area so that it 357 * doesn't overlap with TEXT_BASE. 358 */ 359 #define CONFIG_SYS_TEXT_BASE 0x80008000 360 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 361 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 362 363 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 364 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 365 366 #endif /* __CONFIG_H */ 367