xref: /openbmc/u-boot/include/configs/tao3530.h (revision 1cc95f6e)
1 /*
2  * Configuration settings for the TechNexion TAO-3530 SOM
3  * equipped on Thunder baseboard.
4  *
5  * Edward Lin <linuxfae@technexion.com>
6  * Tapani Utriainen <linuxfae@technexion.com>
7  *
8  * Copyright (C) 2013 Stefan Roese <sr@denx.de>
9  *
10  * SPDX-License-Identifier:	GPL-2.0+
11  */
12 
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15 
16 #define CONFIG_SYS_CACHELINE_SIZE	64
17 
18 /*
19  * High Level Configuration Options
20  */
21 #define CONFIG_OMAP			/* in a TI OMAP core */
22 
23 #define CONFIG_OMAP_GPIO
24 #define CONFIG_OMAP_COMMON
25 /* Common ARM Erratas */
26 #define CONFIG_ARM_ERRATA_454179
27 #define CONFIG_ARM_ERRATA_430973
28 #define CONFIG_ARM_ERRATA_621766
29 
30 #define MACH_TYPE_OMAP3_TAO3530		2836
31 
32 #define CONFIG_SDRC			/* Has an SDRC controller */
33 
34 #include <asm/arch/cpu.h>		/* get chip and board defs */
35 #include <asm/arch/omap.h>
36 
37 /*
38  * Display CPU and Board information
39  */
40 #define CONFIG_DISPLAY_CPUINFO
41 #define CONFIG_DISPLAY_BOARDINFO
42 
43 /* Clock Defines */
44 #define V_OSCK			26000000	/* Clock output from T2 */
45 #define V_SCLK			(V_OSCK >> 1)
46 
47 #define CONFIG_MISC_INIT_R
48 
49 #define CONFIG_CMDLINE_TAG
50 #define CONFIG_SETUP_MEMORY_TAGS
51 #define CONFIG_INITRD_TAG
52 #define CONFIG_REVISION_TAG
53 
54 /*
55  * Size of malloc() pool
56  */
57 #define CONFIG_SYS_MALLOC_LEN		(4 << 20)
58 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
59 
60 /*
61  * Hardware drivers
62  */
63 
64 /*
65  * NS16550 Configuration
66  */
67 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
68 
69 #define CONFIG_SYS_NS16550_SERIAL
70 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
71 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
72 
73 /*
74  * select serial console configuration
75  */
76 #define CONFIG_CONS_INDEX		3
77 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
78 
79 /* allow to overwrite serial and ethaddr */
80 #define CONFIG_ENV_OVERWRITE
81 #define CONFIG_BAUDRATE			115200
82 #define CONFIG_GENERIC_MMC
83 #define CONFIG_MMC
84 #define CONFIG_OMAP_HSMMC
85 #define CONFIG_DOS_PARTITION
86 
87 /* GPIO banks */
88 #define CONFIG_OMAP3_GPIO_2		/* GPIO32 ..63  is in GPIO bank 2 */
89 #define CONFIG_OMAP3_GPIO_3		/* GPIO64 ..95  is in GPIO bank 3 */
90 #define CONFIG_OMAP3_GPIO_4		/* GPIO96 ..127 is in GPIO bank 4 */
91 #define CONFIG_OMAP3_GPIO_5		/* GPIO128..159 is in GPIO bank 5 */
92 #define CONFIG_OMAP3_GPIO_6		/* GPIO160..191 is in GPIO bank 6 */
93 
94 /* commands to include */
95 #define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
96 #define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
97 #define MTDIDS_DEFAULT			"nand0=nand"
98 #define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
99 					"1920k(u-boot),128k(u-boot-env),"\
100 					"4m(kernel),-(fs)"
101 
102 #define CONFIG_CMD_NAND		/* NAND support			*/
103 
104 #define CONFIG_SYS_NO_FLASH
105 #define CONFIG_SYS_I2C
106 #define CONFIG_SYS_I2C_OMAP34XX
107 #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
108 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
109 #define CONFIG_I2C_MULTI_BUS
110 
111 /*
112  * TWL4030
113  */
114 #define CONFIG_TWL4030_POWER
115 #define CONFIG_TWL4030_LED
116 
117 /*
118  * Board NAND Info.
119  */
120 #define CONFIG_NAND_OMAP_GPMC
121 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
122 							/* to access nand */
123 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
124 							/* to access nand at */
125 							/* CS0 */
126 
127 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
128 							/* devices */
129 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
130 /* Environment information */
131 
132 #define CONFIG_EXTRA_ENV_SETTINGS \
133 	"loadaddr=0x82000000\0" \
134 	"console=ttyO2,115200n8\0" \
135 	"mpurate=600\0" \
136 	"dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
137 	"tv_mode=omapfb.mode=tv:ntsc\0" \
138 	"video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
139 	"lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
140 	"extra_options= \0" \
141 	"mmcdev=0\0" \
142 	"mmcroot=/dev/mmcblk0p2 rw\0" \
143 	"mmcrootfstype=ext3 rootwait\0" \
144 	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
145 	"nandrootfstype=ubifs\0" \
146 	"mmcargs=setenv bootargs console=${console} " \
147 		"mpurate=${mpurate} " \
148 		"${video_mode} " \
149 		"root=${mmcroot} " \
150 		"rootfstype=${mmcrootfstype} " \
151 		"${extra_options}\0" \
152 	"nandargs=setenv bootargs console=${console} " \
153 		"mpurate=${mpurate} " \
154 		"${video_mode} " \
155 		"${network_setting} " \
156 		"root=${nandroot} " \
157 		"rootfstype=${nandrootfstype} "\
158 		"${extra_options}\0" \
159 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
160 	"bootscript=echo Running bootscript from mmc ...; " \
161 		"source ${loadaddr}\0" \
162 	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
163 	"mmcboot=echo Booting from mmc ...; " \
164 		"run mmcargs; " \
165 		"bootm ${loadaddr}\0" \
166 	"nandboot=echo Booting from nand ...; " \
167 		"run nandargs; " \
168 		"nand read ${loadaddr} 280000 400000; " \
169 		"bootm ${loadaddr}\0" \
170 
171 #define CONFIG_BOOTCOMMAND \
172 	"if mmc rescan ${mmcdev}; then " \
173 		"if run loadbootscript; then " \
174 			"run bootscript; " \
175 		"else " \
176 			"if run loaduimage; then " \
177 				"run mmcboot; " \
178 			"else run nandboot; " \
179 			"fi; " \
180 		"fi; " \
181 	"else run nandboot; fi"
182 
183 /*
184  * Miscellaneous configurable options
185  */
186 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
187 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
188 
189 /* turn on command-line edit/hist/auto */
190 #define CONFIG_CMDLINE_EDITING
191 #define CONFIG_COMMAND_HISTORY
192 #define CONFIG_AUTO_COMPLETE
193 
194 /* Print Buffer Size */
195 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
196 					sizeof(CONFIG_SYS_PROMPT) + 16)
197 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
198 /* Boot Argument Buffer Size */
199 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
200 
201 #define CONFIG_SYS_ALT_MEMTEST		1
202 #define CONFIG_SYS_MEMTEST_START	(0x82000000)		/* memtest */
203 								/* defaults */
204 #define CONFIG_SYS_MEMTEST_END		(0x83FFFFFF)		/* 64MB */
205 #define CONFIG_SYS_MEMTEST_SCRATCH	(0x81000000)	/* dummy address */
206 
207 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
208 							/* load address */
209 #define CONFIG_SYS_TEXT_BASE		0x80008000
210 
211 /*
212  * OMAP3 has 12 GP timers, they can be driven by the system clock
213  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
214  * This rate is divided by a local divisor.
215  */
216 #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
217 #define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
218 
219 /*
220  * Stack sizes
221  *
222  * The stack sizes are set up in start.S using the settings below
223  */
224 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
225 
226 /*
227  * Physical Memory Map
228  */
229 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
230 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
231 #define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
232 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
233 
234 /*
235  * FLASH and environment organization
236  */
237 
238 /* **** PISMO SUPPORT *** */
239 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
240 #define CONFIG_SYS_FLASH_BASE		NAND_BASE
241 
242 /* Monitor at start of flash */
243 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
244 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
245 
246 #define CONFIG_ENV_IS_IN_NAND		1
247 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
248 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
249 
250 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)
251 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
252 #define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET
253 
254 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
255 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
256 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
257 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
258 					 CONFIG_SYS_INIT_RAM_SIZE - \
259 					 GENERATED_GBL_DATA_SIZE)
260 
261 #define CONFIG_OMAP3_SPI
262 
263 /*
264  * USB
265  *
266  * Currently only EHCI is enabled, the MUSB OTG controller
267  * is not enabled.
268  */
269 
270 /* USB EHCI */
271 #define CONFIG_USB_EHCI
272 #define CONFIG_USB_EHCI_OMAP
273 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	162
274 
275 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
276 #define CONFIG_USB_HOST_ETHER
277 #define CONFIG_USB_ETHER_SMSC95XX
278 
279 #define CONFIG_USB_ETHER
280 #define CONFIG_USB_ETHER_RNDIS
281 #define CONFIG_USB_STORAGE
282 #define CONGIG_CMD_STORAGE
283 
284 /* Defines for SPL */
285 #define CONFIG_SPL_FRAMEWORK
286 #define CONFIG_SPL_NAND_SIMPLE
287 
288 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
289 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
290 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
291 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
292 
293 #define CONFIG_SPL_BOARD_INIT
294 #define CONFIG_SPL_LIBCOMMON_SUPPORT
295 #define CONFIG_SPL_LIBDISK_SUPPORT
296 #define CONFIG_SPL_I2C_SUPPORT
297 #define CONFIG_SPL_LIBGENERIC_SUPPORT
298 #define CONFIG_SPL_MMC_SUPPORT
299 #define CONFIG_SPL_FAT_SUPPORT
300 #define CONFIG_SPL_SERIAL_SUPPORT
301 #define CONFIG_SPL_NAND_SUPPORT
302 #define CONFIG_SPL_NAND_BASE
303 #define CONFIG_SPL_NAND_DRIVERS
304 #define CONFIG_SPL_NAND_ECC
305 #define CONFIG_SPL_GPIO_SUPPORT
306 #define CONFIG_SPL_POWER_SUPPORT
307 #define CONFIG_SPL_OMAP3_ID_NAND
308 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
309 
310 /* NAND boot config */
311 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
312 #define CONFIG_SYS_NAND_PAGE_COUNT	64
313 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
314 #define CONFIG_SYS_NAND_OOBSIZE		64
315 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
316 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
317 /*
318  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
319  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
320  */
321 #define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
322 					 10, 11, 12, 13 }
323 #define CONFIG_SYS_NAND_ECCSIZE		512
324 #define CONFIG_SYS_NAND_ECCBYTES	3
325 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
326 
327 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
328 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
329 
330 #define CONFIG_SPL_TEXT_BASE		0x40200800
331 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
332 
333 /*
334  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
335  * older x-loader implementations. And move the BSS area so that it
336  * doesn't overlap with TEXT_BASE.
337  */
338 #define CONFIG_SYS_TEXT_BASE		0x80008000
339 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
340 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
341 
342 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
343 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
344 
345 #endif /* __CONFIG_H */
346