1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP /* in a TI OMAP core */ 20 21 #define CONFIG_OMAP_GPIO 22 /* Common ARM Erratas */ 23 #define CONFIG_ARM_ERRATA_454179 24 #define CONFIG_ARM_ERRATA_430973 25 #define CONFIG_ARM_ERRATA_621766 26 27 #define MACH_TYPE_OMAP3_TAO3530 2836 28 29 #define CONFIG_SDRC /* Has an SDRC controller */ 30 31 #include <asm/arch/cpu.h> /* get chip and board defs */ 32 #include <asm/arch/omap.h> 33 34 /* Clock Defines */ 35 #define V_OSCK 26000000 /* Clock output from T2 */ 36 #define V_SCLK (V_OSCK >> 1) 37 38 #define CONFIG_MISC_INIT_R 39 40 #define CONFIG_CMDLINE_TAG 41 #define CONFIG_SETUP_MEMORY_TAGS 42 #define CONFIG_INITRD_TAG 43 #define CONFIG_REVISION_TAG 44 45 /* 46 * Size of malloc() pool 47 */ 48 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 49 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 50 51 /* 52 * Hardware drivers 53 */ 54 55 /* 56 * NS16550 Configuration 57 */ 58 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 59 60 #define CONFIG_SYS_NS16550_SERIAL 61 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 62 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 63 64 /* 65 * select serial console configuration 66 */ 67 #define CONFIG_CONS_INDEX 3 68 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 69 70 /* allow to overwrite serial and ethaddr */ 71 #define CONFIG_ENV_OVERWRITE 72 #define CONFIG_BAUDRATE 115200 73 #define CONFIG_GENERIC_MMC 74 #define CONFIG_MMC 75 #define CONFIG_OMAP_HSMMC 76 #define CONFIG_DOS_PARTITION 77 78 /* GPIO banks */ 79 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ 80 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ 81 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ 82 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ 83 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ 84 85 /* commands to include */ 86 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 87 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 88 #define MTDIDS_DEFAULT "nand0=nand" 89 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 90 "1920k(u-boot),128k(u-boot-env),"\ 91 "4m(kernel),-(fs)" 92 93 #define CONFIG_CMD_NAND /* NAND support */ 94 95 #define CONFIG_SYS_NO_FLASH 96 #define CONFIG_SYS_I2C 97 #define CONFIG_SYS_I2C_OMAP34XX 98 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 99 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 100 #define CONFIG_I2C_MULTI_BUS 101 102 /* 103 * TWL4030 104 */ 105 #define CONFIG_TWL4030_POWER 106 #define CONFIG_TWL4030_LED 107 108 /* 109 * Board NAND Info. 110 */ 111 #define CONFIG_NAND_OMAP_GPMC 112 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 113 /* to access nand */ 114 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 115 /* to access nand at */ 116 /* CS0 */ 117 118 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 119 /* devices */ 120 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 121 /* Environment information */ 122 123 #define CONFIG_EXTRA_ENV_SETTINGS \ 124 "loadaddr=0x82000000\0" \ 125 "console=ttyO2,115200n8\0" \ 126 "mpurate=600\0" \ 127 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 128 "tv_mode=omapfb.mode=tv:ntsc\0" \ 129 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 130 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 131 "extra_options= \0" \ 132 "mmcdev=0\0" \ 133 "mmcroot=/dev/mmcblk0p2 rw\0" \ 134 "mmcrootfstype=ext3 rootwait\0" \ 135 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 136 "nandrootfstype=ubifs\0" \ 137 "mmcargs=setenv bootargs console=${console} " \ 138 "mpurate=${mpurate} " \ 139 "${video_mode} " \ 140 "root=${mmcroot} " \ 141 "rootfstype=${mmcrootfstype} " \ 142 "${extra_options}\0" \ 143 "nandargs=setenv bootargs console=${console} " \ 144 "mpurate=${mpurate} " \ 145 "${video_mode} " \ 146 "${network_setting} " \ 147 "root=${nandroot} " \ 148 "rootfstype=${nandrootfstype} "\ 149 "${extra_options}\0" \ 150 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 151 "bootscript=echo Running bootscript from mmc ...; " \ 152 "source ${loadaddr}\0" \ 153 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 154 "mmcboot=echo Booting from mmc ...; " \ 155 "run mmcargs; " \ 156 "bootm ${loadaddr}\0" \ 157 "nandboot=echo Booting from nand ...; " \ 158 "run nandargs; " \ 159 "nand read ${loadaddr} 280000 400000; " \ 160 "bootm ${loadaddr}\0" \ 161 162 #define CONFIG_BOOTCOMMAND \ 163 "if mmc rescan ${mmcdev}; then " \ 164 "if run loadbootscript; then " \ 165 "run bootscript; " \ 166 "else " \ 167 "if run loaduimage; then " \ 168 "run mmcboot; " \ 169 "else run nandboot; " \ 170 "fi; " \ 171 "fi; " \ 172 "else run nandboot; fi" 173 174 /* 175 * Miscellaneous configurable options 176 */ 177 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 178 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 179 180 /* turn on command-line edit/hist/auto */ 181 #define CONFIG_CMDLINE_EDITING 182 #define CONFIG_COMMAND_HISTORY 183 #define CONFIG_AUTO_COMPLETE 184 185 /* Print Buffer Size */ 186 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 187 sizeof(CONFIG_SYS_PROMPT) + 16) 188 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 189 /* Boot Argument Buffer Size */ 190 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 191 192 #define CONFIG_SYS_ALT_MEMTEST 1 193 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 194 /* defaults */ 195 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 196 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 197 198 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 199 /* load address */ 200 #define CONFIG_SYS_TEXT_BASE 0x80008000 201 202 /* 203 * OMAP3 has 12 GP timers, they can be driven by the system clock 204 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 205 * This rate is divided by a local divisor. 206 */ 207 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 208 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 209 210 /* 211 * Stack sizes 212 * 213 * The stack sizes are set up in start.S using the settings below 214 */ 215 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 216 217 /* 218 * Physical Memory Map 219 */ 220 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 221 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 222 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 223 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 224 225 /* 226 * FLASH and environment organization 227 */ 228 229 /* **** PISMO SUPPORT *** */ 230 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 231 #define CONFIG_SYS_FLASH_BASE NAND_BASE 232 233 /* Monitor at start of flash */ 234 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 235 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 236 237 #define CONFIG_ENV_IS_IN_NAND 1 238 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 239 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 240 241 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 242 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 243 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 244 245 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 246 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 247 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 248 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 249 CONFIG_SYS_INIT_RAM_SIZE - \ 250 GENERATED_GBL_DATA_SIZE) 251 252 #define CONFIG_OMAP3_SPI 253 254 /* 255 * USB 256 * 257 * Currently only EHCI is enabled, the MUSB OTG controller 258 * is not enabled. 259 */ 260 261 /* USB EHCI */ 262 #define CONFIG_USB_EHCI 263 #define CONFIG_USB_EHCI_OMAP 264 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 265 266 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 267 #define CONFIG_USB_HOST_ETHER 268 #define CONFIG_USB_ETHER_SMSC95XX 269 270 #define CONFIG_USB_ETHER 271 #define CONFIG_USB_ETHER_RNDIS 272 #define CONGIG_CMD_STORAGE 273 274 /* Defines for SPL */ 275 #define CONFIG_SPL_FRAMEWORK 276 #define CONFIG_SPL_NAND_SIMPLE 277 278 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 279 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 280 281 #define CONFIG_SPL_BOARD_INIT 282 #define CONFIG_SPL_NAND_BASE 283 #define CONFIG_SPL_NAND_DRIVERS 284 #define CONFIG_SPL_NAND_ECC 285 #define CONFIG_SPL_OMAP3_ID_NAND 286 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 287 288 /* NAND boot config */ 289 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 290 #define CONFIG_SYS_NAND_PAGE_COUNT 64 291 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 292 #define CONFIG_SYS_NAND_OOBSIZE 64 293 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 294 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 295 /* 296 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 297 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 298 */ 299 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 300 10, 11, 12, 13 } 301 #define CONFIG_SYS_NAND_ECCSIZE 512 302 #define CONFIG_SYS_NAND_ECCBYTES 3 303 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 304 305 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 306 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 307 308 #define CONFIG_SPL_TEXT_BASE 0x40200800 309 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 310 CONFIG_SPL_TEXT_BASE) 311 312 /* 313 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 314 * older x-loader implementations. And move the BSS area so that it 315 * doesn't overlap with TEXT_BASE. 316 */ 317 #define CONFIG_SYS_TEXT_BASE 0x80008000 318 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 319 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 320 321 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 322 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 323 324 #endif /* __CONFIG_H */ 325