1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __TAM3517_H 11 #define __TAM3517_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 17 #define CONFIG_SYS_TEXT_BASE 0x80008000 18 19 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 20 21 #include <asm/arch/cpu.h> /* get chip and board defs */ 22 #include <asm/arch/omap.h> 23 24 /* Clock Defines */ 25 #define V_OSCK 26000000 /* Clock output from T2 */ 26 #define V_SCLK (V_OSCK >> 1) 27 28 #define CONFIG_MISC_INIT_R 29 30 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 31 #define CONFIG_SETUP_MEMORY_TAGS 32 #define CONFIG_INITRD_TAG 33 #define CONFIG_REVISION_TAG 34 35 /* 36 * Size of malloc() pool 37 */ 38 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 39 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 40 2 * 1024 * 1024) 41 /* 42 * DDR related 43 */ 44 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 45 46 /* 47 * Hardware drivers 48 */ 49 50 /* 51 * NS16550 Configuration 52 */ 53 #define CONFIG_SYS_NS16550_SERIAL 54 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 55 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 56 57 /* 58 * select serial console configuration 59 */ 60 #define CONFIG_CONS_INDEX 1 61 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 62 #define CONFIG_SERIAL1 /* UART1 */ 63 64 /* allow to overwrite serial and ethaddr */ 65 #define CONFIG_ENV_OVERWRITE 66 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 67 115200} 68 /* EHCI */ 69 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 70 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 71 72 /* commands to include */ 73 #define CONFIG_CMD_NAND /* NAND support */ 74 75 #define CONFIG_SYS_I2C 76 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 77 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 78 #define CONFIG_SYS_I2C_OMAP34XX 79 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 80 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 81 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 82 83 /* 84 * Board NAND Info. 85 */ 86 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 87 /* to access */ 88 /* nand at CS0 */ 89 90 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 91 /* NAND devices */ 92 93 #define CONFIG_AUTO_COMPLETE 94 95 /* 96 * Miscellaneous configurable options 97 */ 98 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 99 #define CONFIG_CMDLINE_EDITING 100 #define CONFIG_AUTO_COMPLETE 101 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 102 103 /* Print Buffer Size */ 104 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 105 sizeof(CONFIG_SYS_PROMPT) + 16) 106 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 107 /* args */ 108 /* Boot Argument Buffer Size */ 109 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 110 /* memtest works on */ 111 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 112 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 113 0x01F00000) /* 31MB */ 114 115 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 116 /* address */ 117 118 /* 119 * AM3517 has 12 GP timers, they can be driven by the system clock 120 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 121 * This rate is divided by a local divisor. 122 */ 123 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 124 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 125 126 /* 127 * Physical Memory Map 128 */ 129 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 130 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 131 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 132 133 /* 134 * FLASH and environment organization 135 */ 136 137 /* **** PISMO SUPPORT *** */ 138 #define CONFIG_NAND 139 #define CONFIG_NAND_OMAP_GPMC 140 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 141 142 /* Redundant Environment */ 143 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 144 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 145 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 146 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 147 2 * CONFIG_SYS_ENV_SECT_SIZE) 148 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 149 150 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 151 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 152 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 153 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 154 CONFIG_SYS_INIT_RAM_SIZE - \ 155 GENERATED_GBL_DATA_SIZE) 156 157 /* 158 * ethernet support, EMAC 159 * 160 */ 161 #define CONFIG_DRIVER_TI_EMAC 162 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 163 #define CONFIG_MII 164 #define CONFIG_BOOTP_DNS 165 #define CONFIG_BOOTP_DNS2 166 #define CONFIG_BOOTP_SEND_HOSTNAME 167 #define CONFIG_NET_RETRY_COUNT 10 168 169 /* Defines for SPL */ 170 #define CONFIG_SPL_FRAMEWORK 171 #define CONFIG_SPL_CONSOLE 172 #define CONFIG_SPL_NAND_SIMPLE 173 #define CONFIG_SPL_NAND_SOFTECC 174 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 175 176 #define CONFIG_SPL_NAND_BASE 177 #define CONFIG_SPL_NAND_DRIVERS 178 #define CONFIG_SPL_NAND_ECC 179 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 180 181 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 182 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 183 CONFIG_SPL_TEXT_BASE) 184 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 185 186 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 187 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 188 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 189 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 190 191 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 192 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 193 194 /* FAT */ 195 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 196 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 197 198 /* RAW SD card / eMMC */ 199 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 200 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 201 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 202 203 /* NAND boot config */ 204 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 205 #define CONFIG_SYS_NAND_PAGE_COUNT 64 206 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 207 #define CONFIG_SYS_NAND_OOBSIZE 64 208 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 209 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 210 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 211 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 212 48, 49, 50, 51, 52, 53, 54, 55,\ 213 56, 57, 58, 59, 60, 61, 62, 63} 214 #define CONFIG_SYS_NAND_ECCSIZE 256 215 #define CONFIG_SYS_NAND_ECCBYTES 3 216 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 217 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 218 219 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 220 221 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 222 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 223 224 #define CONFIG_MTD_PARTITIONS 225 #define CONFIG_MTD_DEVICE 226 227 /* Setup MTD for NAND on the SOM */ 228 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 229 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 230 "1m(u-boot),256k(env1)," \ 231 "256k(env2),6m(kernel),-(rootfs)" 232 233 #define CONFIG_TAM3517_SETTINGS \ 234 "netdev=eth0\0" \ 235 "nandargs=setenv bootargs root=${nandroot} " \ 236 "rootfstype=${nandrootfstype}\0" \ 237 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 238 "nfsroot=${serverip}:${rootpath}\0" \ 239 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 240 "addip_sta=setenv bootargs ${bootargs} " \ 241 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 242 ":${hostname}:${netdev}:off panic=1\0" \ 243 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 244 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 245 "else run addip_sta;fi\0" \ 246 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 247 "addtty=setenv bootargs ${bootargs}" \ 248 " console=ttyO0,${baudrate}\0" \ 249 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 250 "loadaddr=82000000\0" \ 251 "kernel_addr_r=82000000\0" \ 252 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 253 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 254 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 255 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 256 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 257 "bootm ${kernel_addr}\0" \ 258 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 259 "nand read ${kernel_addr_r} kernel\0" \ 260 "bootm ${kernel_addr_r}\0" \ 261 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 262 "run nfsargs addip addtty addmtd addmisc;" \ 263 "bootm ${kernel_addr_r}\0" \ 264 "net_self=if run net_self_load;then " \ 265 "run ramargs addip addtty addmtd addmisc;" \ 266 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 267 "else echo Images not loades;fi\0" \ 268 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 269 "load=tftp ${loadaddr} ${u-boot}\0" \ 270 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 271 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 272 "uboot_addr=0x80000\0" \ 273 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 274 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 275 "updatemlo=nandecc hw;nand erase 0 20000;" \ 276 "nand write ${loadaddr} 0 20000\0" \ 277 "upd=if run load;then echo Updating u-boot;if run update;" \ 278 "then echo U-Boot updated;" \ 279 "else echo Error updating u-boot !;" \ 280 "echo Board without bootloader !!;" \ 281 "fi;" \ 282 "else echo U-Boot not downloaded..exiting;fi\0" \ 283 284 /* 285 * this is common code for all TAM3517 boards. 286 * MAC address is stored from manufacturer in 287 * I2C EEPROM 288 */ 289 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 290 /* 291 * The I2C EEPROM on the TAM3517 contains 292 * mac address and production data 293 */ 294 struct tam3517_module_info { 295 char customer[48]; 296 char product[48]; 297 298 /* 299 * bit 0~47 : sequence number 300 * bit 48~55 : week of year, from 0. 301 * bit 56~63 : year 302 */ 303 unsigned long long sequence_number; 304 305 /* 306 * bit 0~7 : revision fixed 307 * bit 8~15 : revision major 308 * bit 16~31 : TNxxx 309 */ 310 unsigned int revision; 311 unsigned char eth_addr[4][8]; 312 unsigned char _rev[100]; 313 }; 314 315 #define TAM3517_READ_EEPROM(info, ret) \ 316 do { \ 317 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 318 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 319 (void *)info, sizeof(*info))) \ 320 ret = 1; \ 321 else \ 322 ret = 0; \ 323 } while (0) 324 325 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 326 do { \ 327 char buf[80], ethname[20]; \ 328 int i; \ 329 memset(buf, 0, sizeof(buf)); \ 330 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 331 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 332 (info)->eth_addr[i][5], \ 333 (info)->eth_addr[i][4], \ 334 (info)->eth_addr[i][3], \ 335 (info)->eth_addr[i][2], \ 336 (info)->eth_addr[i][1], \ 337 (info)->eth_addr[i][0]); \ 338 \ 339 if (i) \ 340 sprintf(ethname, "eth%daddr", i); \ 341 else \ 342 strcpy(ethname, "ethaddr"); \ 343 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 344 setenv(ethname, buf); \ 345 } \ 346 } while (0) 347 348 /* The following macros are taken from Technexion's documentation */ 349 #define TAM3517_sequence_number(info) \ 350 ((info)->sequence_number % 0x1000000000000LL) 351 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 352 #define TAM3517_year(info) ((info)->sequence_number >> 56) 353 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 354 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 355 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 356 357 #define TAM3517_PRINT_SOM_INFO(info) \ 358 do { \ 359 printf("Vendor:%s\n", (info)->customer); \ 360 printf("SOM: %s\n", (info)->product); \ 361 printf("SeqNr: %02llu%02llu%012llu\n", \ 362 TAM3517_year(info), \ 363 TAM3517_week_of_year(info), \ 364 TAM3517_sequence_number(info)); \ 365 printf("Rev: TN%u %u.%u\n", \ 366 TAM3517_revision_tn(info), \ 367 TAM3517_revision_major(info), \ 368 TAM3517_revision_fixed(info)); \ 369 } while (0) 370 371 #endif 372 373 #endif /* __TAM3517_H */ 374