1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc. 20 */ 21 22 #ifndef __TAM3517_H 23 #define __TAM3517_H 24 25 /* 26 * High Level Configuration Options 27 */ 28 #define CONFIG_OMAP /* in a TI OMAP core */ 29 #define CONFIG_OMAP34XX /* which is a 34XX */ 30 #define CONFIG_OMAP_GPIO 31 32 #define CONFIG_SYS_TEXT_BASE 0x80008000 33 34 #define CONFIG_SYS_CACHELINE_SIZE 64 35 36 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 37 38 #include <asm/arch/cpu.h> /* get chip and board defs */ 39 #include <asm/arch/omap3.h> 40 41 /* 42 * Display CPU and Board information 43 */ 44 #define CONFIG_DISPLAY_CPUINFO 45 #define CONFIG_DISPLAY_BOARDINFO 46 47 /* Clock Defines */ 48 #define V_OSCK 26000000 /* Clock output from T2 */ 49 #define V_SCLK (V_OSCK >> 1) 50 51 #define CONFIG_MISC_INIT_R 52 53 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 54 #define CONFIG_SETUP_MEMORY_TAGS 55 #define CONFIG_INITRD_TAG 56 #define CONFIG_REVISION_TAG 57 58 /* 59 * Size of malloc() pool 60 */ 61 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 62 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 63 2 * 1024 * 1024) 64 /* 65 * DDR related 66 */ 67 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ 68 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 69 70 /* 71 * Hardware drivers 72 */ 73 74 /* 75 * NS16550 Configuration 76 */ 77 #define CONFIG_SYS_NS16550 78 #define CONFIG_SYS_NS16550_SERIAL 79 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 80 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 81 82 /* 83 * select serial console configuration 84 */ 85 #define CONFIG_CONS_INDEX 1 86 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 87 #define CONFIG_SERIAL1 /* UART1 */ 88 89 /* allow to overwrite serial and ethaddr */ 90 #define CONFIG_ENV_OVERWRITE 91 #define CONFIG_BAUDRATE 115200 92 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 93 115200} 94 #define CONFIG_MMC 95 #define CONFIG_OMAP_HSMMC 96 #define CONFIG_GENERIC_MMC 97 #define CONFIG_DOS_PARTITION 98 99 /* EHCI */ 100 #define CONFIG_OMAP3_GPIO_5 101 #define CONFIG_USB_EHCI 102 #define CONFIG_USB_EHCI_OMAP 103 #define CONFIG_USB_ULPI 104 #define CONFIG_USB_ULPI_VIEWPORT_OMAP 105 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 106 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 107 #define CONFIG_USB_STORAGE 108 109 /* commands to include */ 110 #include <config_cmd_default.h> 111 112 #define CONFIG_CMD_CACHE 113 #define CONFIG_CMD_DHCP 114 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 115 #define CONFIG_CMD_FAT /* FAT support */ 116 #define CONFIG_CMD_GPIO 117 #define CONFIG_CMD_I2C /* I2C serial bus support */ 118 #define CONFIG_CMD_MII 119 #define CONFIG_CMD_MMC /* MMC support */ 120 #define CONFIG_CMD_NET 121 #define CONFIG_CMD_NFS 122 #define CONFIG_CMD_NAND /* NAND support */ 123 #define CONFIG_CMD_PING 124 #define CONFIG_CMD_USB 125 #define CONFIG_CMD_EEPROM 126 127 #undef CONFIG_CMD_FLASH /* only NAND on the SOM */ 128 #undef CONFIG_CMD_IMLS 129 130 #define CONFIG_SYS_NO_FLASH 131 #define CONFIG_HARD_I2C 132 #define CONFIG_SYS_I2C_SPEED 400000 133 #define CONFIG_SYS_I2C_SLAVE 1 134 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 135 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 136 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 137 #define CONFIG_DRIVER_OMAP34XX_I2C 138 139 140 /* 141 * Board NAND Info. 142 */ 143 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 144 /* to access */ 145 /* nand at CS0 */ 146 147 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 148 /* NAND devices */ 149 150 #define CONFIG_AUTO_COMPLETE 151 152 /* 153 * Miscellaneous configurable options 154 */ 155 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 156 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 157 #define CONFIG_CMDLINE_EDITING 158 #define CONFIG_AUTO_COMPLETE 159 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 160 161 /* Print Buffer Size */ 162 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 163 sizeof(CONFIG_SYS_PROMPT) + 16) 164 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 165 /* args */ 166 /* Boot Argument Buffer Size */ 167 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 168 /* memtest works on */ 169 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 170 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 171 0x01F00000) /* 31MB */ 172 173 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 174 /* address */ 175 176 /* 177 * AM3517 has 12 GP timers, they can be driven by the system clock 178 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 179 * This rate is divided by a local divisor. 180 */ 181 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 182 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 183 #define CONFIG_SYS_HZ 1000 184 185 /* 186 * Physical Memory Map 187 */ 188 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 189 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 190 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 191 192 /* 193 * FLASH and environment organization 194 */ 195 196 /* **** PISMO SUPPORT *** */ 197 198 /* Configure the PISMO */ 199 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 200 201 #define CONFIG_NAND_OMAP_GPMC 202 #define GPMC_NAND_ECC_LP_x16_LAYOUT 203 #define CONFIG_ENV_IS_IN_NAND 204 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 205 206 /* Redundant Environment */ 207 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 208 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 209 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 210 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 211 2 * CONFIG_SYS_ENV_SECT_SIZE) 212 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 213 214 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 215 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 216 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 217 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 218 CONFIG_SYS_INIT_RAM_SIZE - \ 219 GENERATED_GBL_DATA_SIZE) 220 221 /* 222 * ethernet support, EMAC 223 * 224 */ 225 #define CONFIG_DRIVER_TI_EMAC 226 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 227 #define CONFIG_MII 228 #define CONFIG_EMAC_MDIO_PHY_NUM 0 229 #define CONFIG_BOOTP_DEFAULT 230 #define CONFIG_BOOTP_DNS 231 #define CONFIG_BOOTP_DNS2 232 #define CONFIG_BOOTP_SEND_HOSTNAME 233 #define CONFIG_NET_RETRY_COUNT 10 234 235 /* Defines for SPL */ 236 #define CONFIG_SPL 237 #define CONFIG_SPL_FRAMEWORK 238 #define CONFIG_SPL_BOARD_INIT 239 #define CONFIG_SPL_CONSOLE 240 #define CONFIG_SPL_NAND_SIMPLE 241 #define CONFIG_SPL_NAND_SOFTECC 242 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 243 244 #define CONFIG_SPL_LIBCOMMON_SUPPORT 245 #define CONFIG_SPL_LIBDISK_SUPPORT 246 #define CONFIG_SPL_I2C_SUPPORT 247 #define CONFIG_SPL_LIBGENERIC_SUPPORT 248 #define CONFIG_SPL_SERIAL_SUPPORT 249 #define CONFIG_SPL_GPIO_SUPPORT 250 #define CONFIG_SPL_POWER_SUPPORT 251 #define CONFIG_SPL_NAND_SUPPORT 252 #define CONFIG_SPL_NAND_BASE 253 #define CONFIG_SPL_NAND_DRIVERS 254 #define CONFIG_SPL_NAND_ECC 255 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 256 257 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 258 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 259 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 260 261 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 262 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 263 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 264 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 265 266 /* NAND boot config */ 267 #define CONFIG_SYS_NAND_PAGE_COUNT 64 268 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 269 #define CONFIG_SYS_NAND_OOBSIZE 64 270 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 271 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 272 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 273 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 274 48, 49, 50, 51, 52, 53, 54, 55,\ 275 56, 57, 58, 59, 60, 61, 62, 63} 276 #define CONFIG_SYS_NAND_ECCSIZE 256 277 #define CONFIG_SYS_NAND_ECCBYTES 3 278 279 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 280 281 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 282 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 283 284 #define CONFIG_OF_LIBFDT 285 #define CONFIG_FIT 286 #define CONFIG_CMD_UBI 287 #define CONFIG_CMD_UBIFS 288 #define CONFIG_RBTREE 289 #define CONFIG_LZO 290 #define CONFIG_MTD_PARTITIONS 291 #define CONFIG_MTD_DEVICE 292 #define CONFIG_CMD_MTDPARTS 293 294 /* Setup MTD for NAND on the SOM */ 295 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 296 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 297 "1m(u-boot),256k(env1)," \ 298 "256k(env2),6m(kernel),-(rootfs)" 299 300 #define CONFIG_TAM3517_SETTINGS \ 301 "netdev=eth0\0" \ 302 "nandargs=setenv bootargs root=${nandroot} " \ 303 "rootfstype=${nandrootfstype}\0" \ 304 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 305 "nfsroot=${serverip}:${rootpath}\0" \ 306 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 307 "addip_sta=setenv bootargs ${bootargs} " \ 308 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 309 ":${hostname}:${netdev}:off panic=1\0" \ 310 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 311 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 312 "else run addip_sta;fi\0" \ 313 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 314 "addtty=setenv bootargs ${bootargs}" \ 315 " console=ttyO0,${baudrate}\0" \ 316 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 317 "loadaddr=82000000\0" \ 318 "kernel_addr_r=82000000\0" \ 319 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 320 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 321 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 322 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 323 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 324 "bootm ${kernel_addr}\0" \ 325 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 326 "nand read ${kernel_addr_r} kernel\0" \ 327 "bootm ${kernel_addr_r}\0" \ 328 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 329 "run nfsargs addip addtty addmtd addmisc;" \ 330 "bootm ${kernel_addr_r}\0" \ 331 "net_self=if run net_self_load;then " \ 332 "run ramargs addip addtty addmtd addmisc;" \ 333 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 334 "else echo Images not loades;fi\0" \ 335 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 336 "load=tftp ${loadaddr} ${u-boot}\0" \ 337 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 338 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 339 "uboot_addr=0x80000\0" \ 340 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 341 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 342 "updatemlo=nandecc hw;nand erase 0 20000;" \ 343 "nand write ${loadaddr} 0 20000\0" \ 344 "upd=if run load;then echo Updating u-boot;if run update;" \ 345 "then echo U-Boot updated;" \ 346 "else echo Error updating u-boot !;" \ 347 "echo Board without bootloader !!;" \ 348 "fi;" \ 349 "else echo U-Boot not downloaded..exiting;fi\0" \ 350 351 352 /* 353 * this is common code for all TAM3517 boards. 354 * MAC address is stored from manufacturer in 355 * I2C EEPROM 356 */ 357 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 358 /* 359 * The I2C EEPROM on the TAM3517 contains 360 * mac address and production data 361 */ 362 struct tam3517_module_info { 363 char customer[48]; 364 char product[48]; 365 366 /* 367 * bit 0~47 : sequence number 368 * bit 48~55 : week of year, from 0. 369 * bit 56~63 : year 370 */ 371 unsigned long long sequence_number; 372 373 /* 374 * bit 0~7 : revision fixed 375 * bit 8~15 : revision major 376 * bit 16~31 : TNxxx 377 */ 378 unsigned int revision; 379 unsigned char eth_addr[4][8]; 380 unsigned char _rev[100]; 381 }; 382 383 #define TAM3517_READ_EEPROM(info, ret) \ 384 do { \ 385 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \ 386 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 387 (void *)info, sizeof(*info))) \ 388 ret = 1; \ 389 else \ 390 ret = 0; \ 391 } while (0) 392 393 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 394 do { \ 395 char buf[80], ethname[20]; \ 396 int i; \ 397 memset(buf, 0, sizeof(buf)); \ 398 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 399 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 400 (info)->eth_addr[i][5], \ 401 (info)->eth_addr[i][4], \ 402 (info)->eth_addr[i][3], \ 403 (info)->eth_addr[i][2], \ 404 (info)->eth_addr[i][1], \ 405 (info)->eth_addr[i][0]); \ 406 \ 407 if (i) \ 408 sprintf(ethname, "eth%daddr", i); \ 409 else \ 410 sprintf(ethname, "ethaddr"); \ 411 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 412 setenv(ethname, buf); \ 413 } \ 414 } while (0) 415 416 /* The following macros are taken from Technexion's documentation */ 417 #define TAM3517_sequence_number(info) \ 418 ((info)->sequence_number % 0x1000000000000LL) 419 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 420 #define TAM3517_year(info) ((info)->sequence_number >> 56) 421 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 422 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 423 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 424 425 #define TAM3517_PRINT_SOM_INFO(info) \ 426 do { \ 427 printf("Vendor:%s\n", (info)->customer); \ 428 printf("SOM: %s\n", (info)->product); \ 429 printf("SeqNr: %02llu%02llu%012llu\n", \ 430 TAM3517_year(info), \ 431 TAM3517_week_of_year(info), \ 432 TAM3517_sequence_number(info)); \ 433 printf("Rev: TN%u %u.%u\n", \ 434 TAM3517_revision_tn(info), \ 435 TAM3517_revision_major(info), \ 436 TAM3517_revision_fixed(info)); \ 437 } while (0) 438 439 #endif 440 441 #endif /* __TAM3517_H */ 442