1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __TAM3517_H 11 #define __TAM3517_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_OMAP /* in a TI OMAP core */ 17 #define CONFIG_OMAP_GPIO 18 #define CONFIG_OMAP_COMMON 19 #define CONFIG_SYS_GENERIC_BOARD 20 21 #define CONFIG_SYS_TEXT_BASE 0x80008000 22 23 #define CONFIG_SYS_CACHELINE_SIZE 64 24 25 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 26 27 #include <asm/arch/cpu.h> /* get chip and board defs */ 28 #include <asm/arch/omap3.h> 29 30 /* 31 * Display CPU and Board information 32 */ 33 #define CONFIG_DISPLAY_CPUINFO 34 #define CONFIG_DISPLAY_BOARDINFO 35 36 /* Clock Defines */ 37 #define V_OSCK 26000000 /* Clock output from T2 */ 38 #define V_SCLK (V_OSCK >> 1) 39 40 #define CONFIG_MISC_INIT_R 41 42 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 43 #define CONFIG_SETUP_MEMORY_TAGS 44 #define CONFIG_INITRD_TAG 45 #define CONFIG_REVISION_TAG 46 47 /* 48 * Size of malloc() pool 49 */ 50 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 51 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 52 2 * 1024 * 1024) 53 /* 54 * DDR related 55 */ 56 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ 57 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 58 59 /* 60 * Hardware drivers 61 */ 62 63 /* 64 * NS16550 Configuration 65 */ 66 #define CONFIG_SYS_NS16550 67 #define CONFIG_SYS_NS16550_SERIAL 68 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 69 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 70 71 /* 72 * select serial console configuration 73 */ 74 #define CONFIG_CONS_INDEX 1 75 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 76 #define CONFIG_SERIAL1 /* UART1 */ 77 78 /* allow to overwrite serial and ethaddr */ 79 #define CONFIG_ENV_OVERWRITE 80 #define CONFIG_BAUDRATE 115200 81 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 82 115200} 83 #define CONFIG_MMC 84 #define CONFIG_OMAP_HSMMC 85 #define CONFIG_GENERIC_MMC 86 #define CONFIG_DOS_PARTITION 87 88 /* EHCI */ 89 #define CONFIG_OMAP3_GPIO_5 90 #define CONFIG_USB_EHCI 91 #define CONFIG_USB_EHCI_OMAP 92 #define CONFIG_USB_ULPI 93 #define CONFIG_USB_ULPI_VIEWPORT_OMAP 94 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 95 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 96 #define CONFIG_USB_STORAGE 97 98 /* commands to include */ 99 #include <config_cmd_default.h> 100 101 #define CONFIG_CMD_CACHE 102 #define CONFIG_CMD_DHCP 103 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 104 #define CONFIG_CMD_FAT /* FAT support */ 105 #define CONFIG_CMD_GPIO 106 #define CONFIG_CMD_I2C /* I2C serial bus support */ 107 #define CONFIG_CMD_MII 108 #define CONFIG_CMD_MMC /* MMC support */ 109 #define CONFIG_CMD_NET 110 #define CONFIG_CMD_NFS 111 #define CONFIG_CMD_NAND /* NAND support */ 112 #define CONFIG_CMD_PING 113 #define CONFIG_CMD_USB 114 #define CONFIG_CMD_EEPROM 115 116 #undef CONFIG_CMD_FLASH /* only NAND on the SOM */ 117 #undef CONFIG_CMD_IMLS 118 119 #define CONFIG_SYS_NO_FLASH 120 #define CONFIG_SYS_I2C 121 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 122 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 123 #define CONFIG_SYS_I2C_OMAP34XX 124 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 125 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 126 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 127 128 /* 129 * Board NAND Info. 130 */ 131 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 132 /* to access */ 133 /* nand at CS0 */ 134 135 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 136 /* NAND devices */ 137 138 #define CONFIG_AUTO_COMPLETE 139 140 /* 141 * Miscellaneous configurable options 142 */ 143 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 144 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 145 #define CONFIG_CMDLINE_EDITING 146 #define CONFIG_AUTO_COMPLETE 147 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 148 149 /* Print Buffer Size */ 150 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 151 sizeof(CONFIG_SYS_PROMPT) + 16) 152 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 153 /* args */ 154 /* Boot Argument Buffer Size */ 155 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 156 /* memtest works on */ 157 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 158 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 159 0x01F00000) /* 31MB */ 160 161 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 162 /* address */ 163 164 /* 165 * AM3517 has 12 GP timers, they can be driven by the system clock 166 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 167 * This rate is divided by a local divisor. 168 */ 169 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 170 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 171 172 /* 173 * Physical Memory Map 174 */ 175 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 176 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 177 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 178 179 /* 180 * FLASH and environment organization 181 */ 182 183 /* **** PISMO SUPPORT *** */ 184 #define CONFIG_NAND 185 #define CONFIG_NAND_OMAP_GPMC 186 #define CONFIG_ENV_IS_IN_NAND 187 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 188 189 /* Redundant Environment */ 190 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 191 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 192 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 193 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 194 2 * CONFIG_SYS_ENV_SECT_SIZE) 195 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 196 197 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 198 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 199 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 200 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 201 CONFIG_SYS_INIT_RAM_SIZE - \ 202 GENERATED_GBL_DATA_SIZE) 203 204 /* 205 * ethernet support, EMAC 206 * 207 */ 208 #define CONFIG_DRIVER_TI_EMAC 209 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 210 #define CONFIG_MII 211 #define CONFIG_EMAC_MDIO_PHY_NUM 0 212 #define CONFIG_BOOTP_DNS 213 #define CONFIG_BOOTP_DNS2 214 #define CONFIG_BOOTP_SEND_HOSTNAME 215 #define CONFIG_NET_RETRY_COUNT 10 216 217 /* Defines for SPL */ 218 #define CONFIG_SPL_FRAMEWORK 219 #define CONFIG_SPL_BOARD_INIT 220 #define CONFIG_SPL_CONSOLE 221 #define CONFIG_SPL_NAND_SIMPLE 222 #define CONFIG_SPL_NAND_SOFTECC 223 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 224 225 #define CONFIG_SPL_LIBCOMMON_SUPPORT 226 #define CONFIG_SPL_LIBDISK_SUPPORT 227 #define CONFIG_SPL_I2C_SUPPORT 228 #define CONFIG_SPL_LIBGENERIC_SUPPORT 229 #define CONFIG_SPL_SERIAL_SUPPORT 230 #define CONFIG_SPL_GPIO_SUPPORT 231 #define CONFIG_SPL_POWER_SUPPORT 232 #define CONFIG_SPL_NAND_SUPPORT 233 #define CONFIG_SPL_NAND_BASE 234 #define CONFIG_SPL_NAND_DRIVERS 235 #define CONFIG_SPL_NAND_ECC 236 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 237 238 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 239 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 240 241 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 242 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 243 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 244 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 245 246 /* NAND boot config */ 247 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 248 #define CONFIG_SYS_NAND_PAGE_COUNT 64 249 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 250 #define CONFIG_SYS_NAND_OOBSIZE 64 251 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 252 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 253 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 254 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 255 48, 49, 50, 51, 52, 53, 54, 55,\ 256 56, 57, 58, 59, 60, 61, 62, 63} 257 #define CONFIG_SYS_NAND_ECCSIZE 256 258 #define CONFIG_SYS_NAND_ECCBYTES 3 259 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 260 261 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 262 263 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 264 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 265 266 #define CONFIG_OF_LIBFDT 267 #define CONFIG_FIT 268 #define CONFIG_CMD_UBI 269 #define CONFIG_CMD_UBIFS 270 #define CONFIG_RBTREE 271 #define CONFIG_LZO 272 #define CONFIG_MTD_PARTITIONS 273 #define CONFIG_MTD_DEVICE 274 #define CONFIG_CMD_MTDPARTS 275 276 /* Setup MTD for NAND on the SOM */ 277 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 278 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 279 "1m(u-boot),256k(env1)," \ 280 "256k(env2),6m(kernel),-(rootfs)" 281 282 #define CONFIG_TAM3517_SETTINGS \ 283 "netdev=eth0\0" \ 284 "nandargs=setenv bootargs root=${nandroot} " \ 285 "rootfstype=${nandrootfstype}\0" \ 286 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 287 "nfsroot=${serverip}:${rootpath}\0" \ 288 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 289 "addip_sta=setenv bootargs ${bootargs} " \ 290 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 291 ":${hostname}:${netdev}:off panic=1\0" \ 292 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 293 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 294 "else run addip_sta;fi\0" \ 295 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 296 "addtty=setenv bootargs ${bootargs}" \ 297 " console=ttyO0,${baudrate}\0" \ 298 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 299 "loadaddr=82000000\0" \ 300 "kernel_addr_r=82000000\0" \ 301 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 302 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 303 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 304 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 305 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 306 "bootm ${kernel_addr}\0" \ 307 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 308 "nand read ${kernel_addr_r} kernel\0" \ 309 "bootm ${kernel_addr_r}\0" \ 310 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 311 "run nfsargs addip addtty addmtd addmisc;" \ 312 "bootm ${kernel_addr_r}\0" \ 313 "net_self=if run net_self_load;then " \ 314 "run ramargs addip addtty addmtd addmisc;" \ 315 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 316 "else echo Images not loades;fi\0" \ 317 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 318 "load=tftp ${loadaddr} ${u-boot}\0" \ 319 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 320 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 321 "uboot_addr=0x80000\0" \ 322 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 323 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 324 "updatemlo=nandecc hw;nand erase 0 20000;" \ 325 "nand write ${loadaddr} 0 20000\0" \ 326 "upd=if run load;then echo Updating u-boot;if run update;" \ 327 "then echo U-Boot updated;" \ 328 "else echo Error updating u-boot !;" \ 329 "echo Board without bootloader !!;" \ 330 "fi;" \ 331 "else echo U-Boot not downloaded..exiting;fi\0" \ 332 333 334 /* 335 * this is common code for all TAM3517 boards. 336 * MAC address is stored from manufacturer in 337 * I2C EEPROM 338 */ 339 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 340 /* 341 * The I2C EEPROM on the TAM3517 contains 342 * mac address and production data 343 */ 344 struct tam3517_module_info { 345 char customer[48]; 346 char product[48]; 347 348 /* 349 * bit 0~47 : sequence number 350 * bit 48~55 : week of year, from 0. 351 * bit 56~63 : year 352 */ 353 unsigned long long sequence_number; 354 355 /* 356 * bit 0~7 : revision fixed 357 * bit 8~15 : revision major 358 * bit 16~31 : TNxxx 359 */ 360 unsigned int revision; 361 unsigned char eth_addr[4][8]; 362 unsigned char _rev[100]; 363 }; 364 365 #define TAM3517_READ_EEPROM(info, ret) \ 366 do { \ 367 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 368 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 369 (void *)info, sizeof(*info))) \ 370 ret = 1; \ 371 else \ 372 ret = 0; \ 373 } while (0) 374 375 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 376 do { \ 377 char buf[80], ethname[20]; \ 378 int i; \ 379 memset(buf, 0, sizeof(buf)); \ 380 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 381 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 382 (info)->eth_addr[i][5], \ 383 (info)->eth_addr[i][4], \ 384 (info)->eth_addr[i][3], \ 385 (info)->eth_addr[i][2], \ 386 (info)->eth_addr[i][1], \ 387 (info)->eth_addr[i][0]); \ 388 \ 389 if (i) \ 390 sprintf(ethname, "eth%daddr", i); \ 391 else \ 392 sprintf(ethname, "ethaddr"); \ 393 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 394 setenv(ethname, buf); \ 395 } \ 396 } while (0) 397 398 /* The following macros are taken from Technexion's documentation */ 399 #define TAM3517_sequence_number(info) \ 400 ((info)->sequence_number % 0x1000000000000LL) 401 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 402 #define TAM3517_year(info) ((info)->sequence_number >> 56) 403 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 404 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 405 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 406 407 #define TAM3517_PRINT_SOM_INFO(info) \ 408 do { \ 409 printf("Vendor:%s\n", (info)->customer); \ 410 printf("SOM: %s\n", (info)->product); \ 411 printf("SeqNr: %02llu%02llu%012llu\n", \ 412 TAM3517_year(info), \ 413 TAM3517_week_of_year(info), \ 414 TAM3517_sequence_number(info)); \ 415 printf("Rev: TN%u %u.%u\n", \ 416 TAM3517_revision_tn(info), \ 417 TAM3517_revision_major(info), \ 418 TAM3517_revision_fixed(info)); \ 419 } while (0) 420 421 #endif 422 423 #endif /* __TAM3517_H */ 424