1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __TAM3517_H 11 #define __TAM3517_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_OMAP /* in a TI OMAP core */ 17 #define CONFIG_OMAP_GPIO 18 /* Common ARM Erratas */ 19 #define CONFIG_ARM_ERRATA_454179 20 #define CONFIG_ARM_ERRATA_430973 21 #define CONFIG_ARM_ERRATA_621766 22 23 #define CONFIG_SYS_TEXT_BASE 0x80008000 24 25 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 26 27 #include <asm/arch/cpu.h> /* get chip and board defs */ 28 #include <asm/arch/omap.h> 29 30 /* Clock Defines */ 31 #define V_OSCK 26000000 /* Clock output from T2 */ 32 #define V_SCLK (V_OSCK >> 1) 33 34 #define CONFIG_MISC_INIT_R 35 36 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 37 #define CONFIG_SETUP_MEMORY_TAGS 38 #define CONFIG_INITRD_TAG 39 #define CONFIG_REVISION_TAG 40 41 /* 42 * Size of malloc() pool 43 */ 44 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 45 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 46 2 * 1024 * 1024) 47 /* 48 * DDR related 49 */ 50 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ 51 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 52 53 /* 54 * Hardware drivers 55 */ 56 57 /* 58 * NS16550 Configuration 59 */ 60 #define CONFIG_SYS_NS16550_SERIAL 61 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 62 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 63 64 /* 65 * select serial console configuration 66 */ 67 #define CONFIG_CONS_INDEX 1 68 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 69 #define CONFIG_SERIAL1 /* UART1 */ 70 71 /* allow to overwrite serial and ethaddr */ 72 #define CONFIG_ENV_OVERWRITE 73 #define CONFIG_BAUDRATE 115200 74 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 75 115200} 76 #define CONFIG_GENERIC_MMC 77 78 /* EHCI */ 79 #define CONFIG_OMAP3_GPIO_5 80 #define CONFIG_USB_EHCI 81 #define CONFIG_USB_EHCI_OMAP 82 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 83 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 84 85 /* commands to include */ 86 #define CONFIG_CMD_NAND /* NAND support */ 87 #define CONFIG_CMD_EEPROM 88 89 #define CONFIG_SYS_NO_FLASH 90 #define CONFIG_SYS_I2C 91 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 92 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 93 #define CONFIG_SYS_I2C_OMAP34XX 94 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 95 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 96 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 97 98 /* 99 * Board NAND Info. 100 */ 101 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 102 /* to access */ 103 /* nand at CS0 */ 104 105 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 106 /* NAND devices */ 107 108 #define CONFIG_AUTO_COMPLETE 109 110 /* 111 * Miscellaneous configurable options 112 */ 113 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 114 #define CONFIG_CMDLINE_EDITING 115 #define CONFIG_AUTO_COMPLETE 116 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 117 118 /* Print Buffer Size */ 119 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 120 sizeof(CONFIG_SYS_PROMPT) + 16) 121 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 122 /* args */ 123 /* Boot Argument Buffer Size */ 124 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 125 /* memtest works on */ 126 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 127 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 128 0x01F00000) /* 31MB */ 129 130 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 131 /* address */ 132 133 /* 134 * AM3517 has 12 GP timers, they can be driven by the system clock 135 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 136 * This rate is divided by a local divisor. 137 */ 138 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 139 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 140 141 /* 142 * Physical Memory Map 143 */ 144 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 145 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 146 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 147 148 /* 149 * FLASH and environment organization 150 */ 151 152 /* **** PISMO SUPPORT *** */ 153 #define CONFIG_NAND 154 #define CONFIG_NAND_OMAP_GPMC 155 #define CONFIG_ENV_IS_IN_NAND 156 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 157 158 /* Redundant Environment */ 159 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 160 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 161 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 162 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 163 2 * CONFIG_SYS_ENV_SECT_SIZE) 164 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 165 166 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 167 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 168 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 169 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 170 CONFIG_SYS_INIT_RAM_SIZE - \ 171 GENERATED_GBL_DATA_SIZE) 172 173 /* 174 * ethernet support, EMAC 175 * 176 */ 177 #define CONFIG_DRIVER_TI_EMAC 178 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 179 #define CONFIG_MII 180 #define CONFIG_EMAC_MDIO_PHY_NUM 0 181 #define CONFIG_BOOTP_DNS 182 #define CONFIG_BOOTP_DNS2 183 #define CONFIG_BOOTP_SEND_HOSTNAME 184 #define CONFIG_NET_RETRY_COUNT 10 185 186 /* Defines for SPL */ 187 #define CONFIG_SPL_FRAMEWORK 188 #define CONFIG_SPL_BOARD_INIT 189 #define CONFIG_SPL_CONSOLE 190 #define CONFIG_SPL_NAND_SIMPLE 191 #define CONFIG_SPL_NAND_SOFTECC 192 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 193 194 #define CONFIG_SPL_NAND_BASE 195 #define CONFIG_SPL_NAND_DRIVERS 196 #define CONFIG_SPL_NAND_ECC 197 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 198 199 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 200 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 201 CONFIG_SPL_TEXT_BASE) 202 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 203 204 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 205 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 206 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 207 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 208 209 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 210 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 211 212 /* FAT */ 213 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 214 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 215 216 /* RAW SD card / eMMC */ 217 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 218 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 219 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 220 221 /* NAND boot config */ 222 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 223 #define CONFIG_SYS_NAND_PAGE_COUNT 64 224 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 225 #define CONFIG_SYS_NAND_OOBSIZE 64 226 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 227 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 228 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 229 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 230 48, 49, 50, 51, 52, 53, 54, 55,\ 231 56, 57, 58, 59, 60, 61, 62, 63} 232 #define CONFIG_SYS_NAND_ECCSIZE 256 233 #define CONFIG_SYS_NAND_ECCBYTES 3 234 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 235 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 236 237 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 238 239 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 240 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 241 242 #define CONFIG_CMD_UBIFS 243 #define CONFIG_RBTREE 244 #define CONFIG_LZO 245 #define CONFIG_MTD_PARTITIONS 246 #define CONFIG_MTD_DEVICE 247 #define CONFIG_CMD_MTDPARTS 248 249 /* Setup MTD for NAND on the SOM */ 250 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 251 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 252 "1m(u-boot),256k(env1)," \ 253 "256k(env2),6m(kernel),-(rootfs)" 254 255 #define CONFIG_TAM3517_SETTINGS \ 256 "netdev=eth0\0" \ 257 "nandargs=setenv bootargs root=${nandroot} " \ 258 "rootfstype=${nandrootfstype}\0" \ 259 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 260 "nfsroot=${serverip}:${rootpath}\0" \ 261 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 262 "addip_sta=setenv bootargs ${bootargs} " \ 263 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 264 ":${hostname}:${netdev}:off panic=1\0" \ 265 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 266 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 267 "else run addip_sta;fi\0" \ 268 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 269 "addtty=setenv bootargs ${bootargs}" \ 270 " console=ttyO0,${baudrate}\0" \ 271 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 272 "loadaddr=82000000\0" \ 273 "kernel_addr_r=82000000\0" \ 274 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 275 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 276 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 277 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 278 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 279 "bootm ${kernel_addr}\0" \ 280 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 281 "nand read ${kernel_addr_r} kernel\0" \ 282 "bootm ${kernel_addr_r}\0" \ 283 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 284 "run nfsargs addip addtty addmtd addmisc;" \ 285 "bootm ${kernel_addr_r}\0" \ 286 "net_self=if run net_self_load;then " \ 287 "run ramargs addip addtty addmtd addmisc;" \ 288 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 289 "else echo Images not loades;fi\0" \ 290 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 291 "load=tftp ${loadaddr} ${u-boot}\0" \ 292 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 293 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 294 "uboot_addr=0x80000\0" \ 295 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 296 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 297 "updatemlo=nandecc hw;nand erase 0 20000;" \ 298 "nand write ${loadaddr} 0 20000\0" \ 299 "upd=if run load;then echo Updating u-boot;if run update;" \ 300 "then echo U-Boot updated;" \ 301 "else echo Error updating u-boot !;" \ 302 "echo Board without bootloader !!;" \ 303 "fi;" \ 304 "else echo U-Boot not downloaded..exiting;fi\0" \ 305 306 /* 307 * this is common code for all TAM3517 boards. 308 * MAC address is stored from manufacturer in 309 * I2C EEPROM 310 */ 311 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 312 /* 313 * The I2C EEPROM on the TAM3517 contains 314 * mac address and production data 315 */ 316 struct tam3517_module_info { 317 char customer[48]; 318 char product[48]; 319 320 /* 321 * bit 0~47 : sequence number 322 * bit 48~55 : week of year, from 0. 323 * bit 56~63 : year 324 */ 325 unsigned long long sequence_number; 326 327 /* 328 * bit 0~7 : revision fixed 329 * bit 8~15 : revision major 330 * bit 16~31 : TNxxx 331 */ 332 unsigned int revision; 333 unsigned char eth_addr[4][8]; 334 unsigned char _rev[100]; 335 }; 336 337 #define TAM3517_READ_EEPROM(info, ret) \ 338 do { \ 339 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 340 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 341 (void *)info, sizeof(*info))) \ 342 ret = 1; \ 343 else \ 344 ret = 0; \ 345 } while (0) 346 347 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 348 do { \ 349 char buf[80], ethname[20]; \ 350 int i; \ 351 memset(buf, 0, sizeof(buf)); \ 352 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 353 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 354 (info)->eth_addr[i][5], \ 355 (info)->eth_addr[i][4], \ 356 (info)->eth_addr[i][3], \ 357 (info)->eth_addr[i][2], \ 358 (info)->eth_addr[i][1], \ 359 (info)->eth_addr[i][0]); \ 360 \ 361 if (i) \ 362 sprintf(ethname, "eth%daddr", i); \ 363 else \ 364 strcpy(ethname, "ethaddr"); \ 365 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 366 setenv(ethname, buf); \ 367 } \ 368 } while (0) 369 370 /* The following macros are taken from Technexion's documentation */ 371 #define TAM3517_sequence_number(info) \ 372 ((info)->sequence_number % 0x1000000000000LL) 373 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 374 #define TAM3517_year(info) ((info)->sequence_number >> 56) 375 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 376 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 377 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 378 379 #define TAM3517_PRINT_SOM_INFO(info) \ 380 do { \ 381 printf("Vendor:%s\n", (info)->customer); \ 382 printf("SOM: %s\n", (info)->product); \ 383 printf("SeqNr: %02llu%02llu%012llu\n", \ 384 TAM3517_year(info), \ 385 TAM3517_week_of_year(info), \ 386 TAM3517_sequence_number(info)); \ 387 printf("Rev: TN%u %u.%u\n", \ 388 TAM3517_revision_tn(info), \ 389 TAM3517_revision_major(info), \ 390 TAM3517_revision_fixed(info)); \ 391 } while (0) 392 393 #endif 394 395 #endif /* __TAM3517_H */ 396