1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __TAM3517_H 11 #define __TAM3517_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_OMAP /* in a TI OMAP core */ 17 #define CONFIG_OMAP34XX /* which is a 34XX */ 18 #define CONFIG_OMAP_GPIO 19 #define CONFIG_OMAP_COMMON 20 #define CONFIG_SYS_GENERIC_BOARD 21 22 #define CONFIG_SYS_TEXT_BASE 0x80008000 23 24 #define CONFIG_SYS_CACHELINE_SIZE 64 25 26 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 27 28 #include <asm/arch/cpu.h> /* get chip and board defs */ 29 #include <asm/arch/omap3.h> 30 31 /* 32 * Display CPU and Board information 33 */ 34 #define CONFIG_DISPLAY_CPUINFO 35 #define CONFIG_DISPLAY_BOARDINFO 36 37 /* Clock Defines */ 38 #define V_OSCK 26000000 /* Clock output from T2 */ 39 #define V_SCLK (V_OSCK >> 1) 40 41 #define CONFIG_MISC_INIT_R 42 43 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 44 #define CONFIG_SETUP_MEMORY_TAGS 45 #define CONFIG_INITRD_TAG 46 #define CONFIG_REVISION_TAG 47 48 /* 49 * Size of malloc() pool 50 */ 51 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 52 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 53 2 * 1024 * 1024) 54 /* 55 * DDR related 56 */ 57 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ 58 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 59 60 /* 61 * Hardware drivers 62 */ 63 64 /* 65 * NS16550 Configuration 66 */ 67 #define CONFIG_SYS_NS16550 68 #define CONFIG_SYS_NS16550_SERIAL 69 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 70 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 71 72 /* 73 * select serial console configuration 74 */ 75 #define CONFIG_CONS_INDEX 1 76 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 77 #define CONFIG_SERIAL1 /* UART1 */ 78 79 /* allow to overwrite serial and ethaddr */ 80 #define CONFIG_ENV_OVERWRITE 81 #define CONFIG_BAUDRATE 115200 82 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 83 115200} 84 #define CONFIG_MMC 85 #define CONFIG_OMAP_HSMMC 86 #define CONFIG_GENERIC_MMC 87 #define CONFIG_DOS_PARTITION 88 89 /* EHCI */ 90 #define CONFIG_OMAP3_GPIO_5 91 #define CONFIG_USB_EHCI 92 #define CONFIG_USB_EHCI_OMAP 93 #define CONFIG_USB_ULPI 94 #define CONFIG_USB_ULPI_VIEWPORT_OMAP 95 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 96 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 97 #define CONFIG_USB_STORAGE 98 99 /* commands to include */ 100 #include <config_cmd_default.h> 101 102 #define CONFIG_CMD_CACHE 103 #define CONFIG_CMD_DHCP 104 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 105 #define CONFIG_CMD_FAT /* FAT support */ 106 #define CONFIG_CMD_GPIO 107 #define CONFIG_CMD_I2C /* I2C serial bus support */ 108 #define CONFIG_CMD_MII 109 #define CONFIG_CMD_MMC /* MMC support */ 110 #define CONFIG_CMD_NET 111 #define CONFIG_CMD_NFS 112 #define CONFIG_CMD_NAND /* NAND support */ 113 #define CONFIG_CMD_PING 114 #define CONFIG_CMD_USB 115 #define CONFIG_CMD_EEPROM 116 117 #undef CONFIG_CMD_FLASH /* only NAND on the SOM */ 118 #undef CONFIG_CMD_IMLS 119 120 #define CONFIG_SYS_NO_FLASH 121 #define CONFIG_SYS_I2C 122 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 123 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 124 #define CONFIG_SYS_I2C_OMAP34XX 125 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 126 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 127 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 128 129 /* 130 * Board NAND Info. 131 */ 132 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 133 /* to access */ 134 /* nand at CS0 */ 135 136 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 137 /* NAND devices */ 138 139 #define CONFIG_AUTO_COMPLETE 140 141 /* 142 * Miscellaneous configurable options 143 */ 144 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 145 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 146 #define CONFIG_CMDLINE_EDITING 147 #define CONFIG_AUTO_COMPLETE 148 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 149 150 /* Print Buffer Size */ 151 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 152 sizeof(CONFIG_SYS_PROMPT) + 16) 153 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 154 /* args */ 155 /* Boot Argument Buffer Size */ 156 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 157 /* memtest works on */ 158 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 159 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 160 0x01F00000) /* 31MB */ 161 162 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 163 /* address */ 164 165 /* 166 * AM3517 has 12 GP timers, they can be driven by the system clock 167 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 168 * This rate is divided by a local divisor. 169 */ 170 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 171 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 172 173 /* 174 * Physical Memory Map 175 */ 176 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 177 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 178 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 179 180 /* 181 * FLASH and environment organization 182 */ 183 184 /* **** PISMO SUPPORT *** */ 185 #define CONFIG_NAND 186 #define CONFIG_NAND_OMAP_GPMC 187 #define CONFIG_ENV_IS_IN_NAND 188 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 189 190 /* Redundant Environment */ 191 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 192 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 193 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 194 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 195 2 * CONFIG_SYS_ENV_SECT_SIZE) 196 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 197 198 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 199 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 200 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 201 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 202 CONFIG_SYS_INIT_RAM_SIZE - \ 203 GENERATED_GBL_DATA_SIZE) 204 205 /* 206 * ethernet support, EMAC 207 * 208 */ 209 #define CONFIG_DRIVER_TI_EMAC 210 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 211 #define CONFIG_MII 212 #define CONFIG_EMAC_MDIO_PHY_NUM 0 213 #define CONFIG_BOOTP_DNS 214 #define CONFIG_BOOTP_DNS2 215 #define CONFIG_BOOTP_SEND_HOSTNAME 216 #define CONFIG_NET_RETRY_COUNT 10 217 218 /* Defines for SPL */ 219 #define CONFIG_SPL_FRAMEWORK 220 #define CONFIG_SPL_BOARD_INIT 221 #define CONFIG_SPL_CONSOLE 222 #define CONFIG_SPL_NAND_SIMPLE 223 #define CONFIG_SPL_NAND_SOFTECC 224 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 225 226 #define CONFIG_SPL_LIBCOMMON_SUPPORT 227 #define CONFIG_SPL_LIBDISK_SUPPORT 228 #define CONFIG_SPL_I2C_SUPPORT 229 #define CONFIG_SPL_LIBGENERIC_SUPPORT 230 #define CONFIG_SPL_SERIAL_SUPPORT 231 #define CONFIG_SPL_GPIO_SUPPORT 232 #define CONFIG_SPL_POWER_SUPPORT 233 #define CONFIG_SPL_NAND_SUPPORT 234 #define CONFIG_SPL_NAND_BASE 235 #define CONFIG_SPL_NAND_DRIVERS 236 #define CONFIG_SPL_NAND_ECC 237 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 238 239 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 240 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 241 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 242 243 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 244 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 245 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 246 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 247 248 /* NAND boot config */ 249 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 250 #define CONFIG_SYS_NAND_PAGE_COUNT 64 251 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 252 #define CONFIG_SYS_NAND_OOBSIZE 64 253 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 254 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 255 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 256 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 257 48, 49, 50, 51, 52, 53, 54, 55,\ 258 56, 57, 58, 59, 60, 61, 62, 63} 259 #define CONFIG_SYS_NAND_ECCSIZE 256 260 #define CONFIG_SYS_NAND_ECCBYTES 3 261 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 262 263 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 264 265 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 266 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 267 268 #define CONFIG_OF_LIBFDT 269 #define CONFIG_FIT 270 #define CONFIG_CMD_UBI 271 #define CONFIG_CMD_UBIFS 272 #define CONFIG_RBTREE 273 #define CONFIG_LZO 274 #define CONFIG_MTD_PARTITIONS 275 #define CONFIG_MTD_DEVICE 276 #define CONFIG_CMD_MTDPARTS 277 278 /* Setup MTD for NAND on the SOM */ 279 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 280 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 281 "1m(u-boot),256k(env1)," \ 282 "256k(env2),6m(kernel),-(rootfs)" 283 284 #define CONFIG_TAM3517_SETTINGS \ 285 "netdev=eth0\0" \ 286 "nandargs=setenv bootargs root=${nandroot} " \ 287 "rootfstype=${nandrootfstype}\0" \ 288 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 289 "nfsroot=${serverip}:${rootpath}\0" \ 290 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 291 "addip_sta=setenv bootargs ${bootargs} " \ 292 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 293 ":${hostname}:${netdev}:off panic=1\0" \ 294 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 295 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 296 "else run addip_sta;fi\0" \ 297 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 298 "addtty=setenv bootargs ${bootargs}" \ 299 " console=ttyO0,${baudrate}\0" \ 300 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 301 "loadaddr=82000000\0" \ 302 "kernel_addr_r=82000000\0" \ 303 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 304 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 305 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 306 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 307 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 308 "bootm ${kernel_addr}\0" \ 309 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 310 "nand read ${kernel_addr_r} kernel\0" \ 311 "bootm ${kernel_addr_r}\0" \ 312 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 313 "run nfsargs addip addtty addmtd addmisc;" \ 314 "bootm ${kernel_addr_r}\0" \ 315 "net_self=if run net_self_load;then " \ 316 "run ramargs addip addtty addmtd addmisc;" \ 317 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 318 "else echo Images not loades;fi\0" \ 319 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 320 "load=tftp ${loadaddr} ${u-boot}\0" \ 321 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 322 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 323 "uboot_addr=0x80000\0" \ 324 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 325 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 326 "updatemlo=nandecc hw;nand erase 0 20000;" \ 327 "nand write ${loadaddr} 0 20000\0" \ 328 "upd=if run load;then echo Updating u-boot;if run update;" \ 329 "then echo U-Boot updated;" \ 330 "else echo Error updating u-boot !;" \ 331 "echo Board without bootloader !!;" \ 332 "fi;" \ 333 "else echo U-Boot not downloaded..exiting;fi\0" \ 334 335 336 /* 337 * this is common code for all TAM3517 boards. 338 * MAC address is stored from manufacturer in 339 * I2C EEPROM 340 */ 341 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 342 /* 343 * The I2C EEPROM on the TAM3517 contains 344 * mac address and production data 345 */ 346 struct tam3517_module_info { 347 char customer[48]; 348 char product[48]; 349 350 /* 351 * bit 0~47 : sequence number 352 * bit 48~55 : week of year, from 0. 353 * bit 56~63 : year 354 */ 355 unsigned long long sequence_number; 356 357 /* 358 * bit 0~7 : revision fixed 359 * bit 8~15 : revision major 360 * bit 16~31 : TNxxx 361 */ 362 unsigned int revision; 363 unsigned char eth_addr[4][8]; 364 unsigned char _rev[100]; 365 }; 366 367 #define TAM3517_READ_EEPROM(info, ret) \ 368 do { \ 369 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 370 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 371 (void *)info, sizeof(*info))) \ 372 ret = 1; \ 373 else \ 374 ret = 0; \ 375 } while (0) 376 377 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 378 do { \ 379 char buf[80], ethname[20]; \ 380 int i; \ 381 memset(buf, 0, sizeof(buf)); \ 382 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 383 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 384 (info)->eth_addr[i][5], \ 385 (info)->eth_addr[i][4], \ 386 (info)->eth_addr[i][3], \ 387 (info)->eth_addr[i][2], \ 388 (info)->eth_addr[i][1], \ 389 (info)->eth_addr[i][0]); \ 390 \ 391 if (i) \ 392 sprintf(ethname, "eth%daddr", i); \ 393 else \ 394 sprintf(ethname, "ethaddr"); \ 395 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 396 setenv(ethname, buf); \ 397 } \ 398 } while (0) 399 400 /* The following macros are taken from Technexion's documentation */ 401 #define TAM3517_sequence_number(info) \ 402 ((info)->sequence_number % 0x1000000000000LL) 403 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 404 #define TAM3517_year(info) ((info)->sequence_number >> 56) 405 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 406 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 407 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 408 409 #define TAM3517_PRINT_SOM_INFO(info) \ 410 do { \ 411 printf("Vendor:%s\n", (info)->customer); \ 412 printf("SOM: %s\n", (info)->product); \ 413 printf("SeqNr: %02llu%02llu%012llu\n", \ 414 TAM3517_year(info), \ 415 TAM3517_week_of_year(info), \ 416 TAM3517_sequence_number(info)); \ 417 printf("Rev: TN%u %u.%u\n", \ 418 TAM3517_revision_tn(info), \ 419 TAM3517_revision_major(info), \ 420 TAM3517_revision_fixed(info)); \ 421 } while (0) 422 423 #endif 424 425 #endif /* __TAM3517_H */ 426