1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __TAM3517_H 11 #define __TAM3517_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_OMAP /* in a TI OMAP core */ 17 #define CONFIG_OMAP_GPIO 18 /* Common ARM Erratas */ 19 #define CONFIG_ARM_ERRATA_454179 20 #define CONFIG_ARM_ERRATA_430973 21 #define CONFIG_ARM_ERRATA_621766 22 23 #define CONFIG_SYS_TEXT_BASE 0x80008000 24 25 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 26 27 #include <asm/arch/cpu.h> /* get chip and board defs */ 28 #include <asm/arch/omap.h> 29 30 /* Clock Defines */ 31 #define V_OSCK 26000000 /* Clock output from T2 */ 32 #define V_SCLK (V_OSCK >> 1) 33 34 #define CONFIG_MISC_INIT_R 35 36 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 37 #define CONFIG_SETUP_MEMORY_TAGS 38 #define CONFIG_INITRD_TAG 39 #define CONFIG_REVISION_TAG 40 41 /* 42 * Size of malloc() pool 43 */ 44 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 45 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 46 2 * 1024 * 1024) 47 /* 48 * DDR related 49 */ 50 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ 51 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 52 53 /* 54 * Hardware drivers 55 */ 56 57 /* 58 * NS16550 Configuration 59 */ 60 #define CONFIG_SYS_NS16550_SERIAL 61 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 62 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 63 64 /* 65 * select serial console configuration 66 */ 67 #define CONFIG_CONS_INDEX 1 68 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 69 #define CONFIG_SERIAL1 /* UART1 */ 70 71 /* allow to overwrite serial and ethaddr */ 72 #define CONFIG_ENV_OVERWRITE 73 #define CONFIG_BAUDRATE 115200 74 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 75 115200} 76 /* EHCI */ 77 #define CONFIG_OMAP3_GPIO_5 78 #define CONFIG_USB_EHCI 79 #define CONFIG_USB_EHCI_OMAP 80 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 81 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 82 83 /* commands to include */ 84 #define CONFIG_CMD_NAND /* NAND support */ 85 #define CONFIG_CMD_EEPROM 86 87 #define CONFIG_SYS_NO_FLASH 88 #define CONFIG_SYS_I2C 89 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 90 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 91 #define CONFIG_SYS_I2C_OMAP34XX 92 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 93 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 94 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 95 96 /* 97 * Board NAND Info. 98 */ 99 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 100 /* to access */ 101 /* nand at CS0 */ 102 103 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 104 /* NAND devices */ 105 106 #define CONFIG_AUTO_COMPLETE 107 108 /* 109 * Miscellaneous configurable options 110 */ 111 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 112 #define CONFIG_CMDLINE_EDITING 113 #define CONFIG_AUTO_COMPLETE 114 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 115 116 /* Print Buffer Size */ 117 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 118 sizeof(CONFIG_SYS_PROMPT) + 16) 119 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 120 /* args */ 121 /* Boot Argument Buffer Size */ 122 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 123 /* memtest works on */ 124 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 125 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 126 0x01F00000) /* 31MB */ 127 128 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 129 /* address */ 130 131 /* 132 * AM3517 has 12 GP timers, they can be driven by the system clock 133 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 134 * This rate is divided by a local divisor. 135 */ 136 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 137 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 138 139 /* 140 * Physical Memory Map 141 */ 142 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 143 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 144 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 145 146 /* 147 * FLASH and environment organization 148 */ 149 150 /* **** PISMO SUPPORT *** */ 151 #define CONFIG_NAND 152 #define CONFIG_NAND_OMAP_GPMC 153 #define CONFIG_ENV_IS_IN_NAND 154 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 155 156 /* Redundant Environment */ 157 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 158 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 159 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 160 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 161 2 * CONFIG_SYS_ENV_SECT_SIZE) 162 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 163 164 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 165 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 166 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 167 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 168 CONFIG_SYS_INIT_RAM_SIZE - \ 169 GENERATED_GBL_DATA_SIZE) 170 171 /* 172 * ethernet support, EMAC 173 * 174 */ 175 #define CONFIG_DRIVER_TI_EMAC 176 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 177 #define CONFIG_MII 178 #define CONFIG_EMAC_MDIO_PHY_NUM 0 179 #define CONFIG_BOOTP_DNS 180 #define CONFIG_BOOTP_DNS2 181 #define CONFIG_BOOTP_SEND_HOSTNAME 182 #define CONFIG_NET_RETRY_COUNT 10 183 184 /* Defines for SPL */ 185 #define CONFIG_SPL_FRAMEWORK 186 #define CONFIG_SPL_BOARD_INIT 187 #define CONFIG_SPL_CONSOLE 188 #define CONFIG_SPL_NAND_SIMPLE 189 #define CONFIG_SPL_NAND_SOFTECC 190 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 191 192 #define CONFIG_SPL_NAND_BASE 193 #define CONFIG_SPL_NAND_DRIVERS 194 #define CONFIG_SPL_NAND_ECC 195 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 196 197 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 198 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 199 CONFIG_SPL_TEXT_BASE) 200 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 201 202 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 203 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 204 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 205 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 206 207 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 208 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 209 210 /* FAT */ 211 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 212 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 213 214 /* RAW SD card / eMMC */ 215 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 216 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 217 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 218 219 /* NAND boot config */ 220 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 221 #define CONFIG_SYS_NAND_PAGE_COUNT 64 222 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 223 #define CONFIG_SYS_NAND_OOBSIZE 64 224 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 225 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 226 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 227 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 228 48, 49, 50, 51, 52, 53, 54, 55,\ 229 56, 57, 58, 59, 60, 61, 62, 63} 230 #define CONFIG_SYS_NAND_ECCSIZE 256 231 #define CONFIG_SYS_NAND_ECCBYTES 3 232 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 233 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 234 235 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 236 237 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 238 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 239 240 #define CONFIG_CMD_UBIFS 241 #define CONFIG_RBTREE 242 #define CONFIG_LZO 243 #define CONFIG_MTD_PARTITIONS 244 #define CONFIG_MTD_DEVICE 245 #define CONFIG_CMD_MTDPARTS 246 247 /* Setup MTD for NAND on the SOM */ 248 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 249 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 250 "1m(u-boot),256k(env1)," \ 251 "256k(env2),6m(kernel),-(rootfs)" 252 253 #define CONFIG_TAM3517_SETTINGS \ 254 "netdev=eth0\0" \ 255 "nandargs=setenv bootargs root=${nandroot} " \ 256 "rootfstype=${nandrootfstype}\0" \ 257 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 258 "nfsroot=${serverip}:${rootpath}\0" \ 259 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 260 "addip_sta=setenv bootargs ${bootargs} " \ 261 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 262 ":${hostname}:${netdev}:off panic=1\0" \ 263 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 264 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 265 "else run addip_sta;fi\0" \ 266 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 267 "addtty=setenv bootargs ${bootargs}" \ 268 " console=ttyO0,${baudrate}\0" \ 269 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 270 "loadaddr=82000000\0" \ 271 "kernel_addr_r=82000000\0" \ 272 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 273 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 274 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 275 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 276 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 277 "bootm ${kernel_addr}\0" \ 278 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 279 "nand read ${kernel_addr_r} kernel\0" \ 280 "bootm ${kernel_addr_r}\0" \ 281 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 282 "run nfsargs addip addtty addmtd addmisc;" \ 283 "bootm ${kernel_addr_r}\0" \ 284 "net_self=if run net_self_load;then " \ 285 "run ramargs addip addtty addmtd addmisc;" \ 286 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 287 "else echo Images not loades;fi\0" \ 288 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 289 "load=tftp ${loadaddr} ${u-boot}\0" \ 290 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 291 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 292 "uboot_addr=0x80000\0" \ 293 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 294 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 295 "updatemlo=nandecc hw;nand erase 0 20000;" \ 296 "nand write ${loadaddr} 0 20000\0" \ 297 "upd=if run load;then echo Updating u-boot;if run update;" \ 298 "then echo U-Boot updated;" \ 299 "else echo Error updating u-boot !;" \ 300 "echo Board without bootloader !!;" \ 301 "fi;" \ 302 "else echo U-Boot not downloaded..exiting;fi\0" \ 303 304 /* 305 * this is common code for all TAM3517 boards. 306 * MAC address is stored from manufacturer in 307 * I2C EEPROM 308 */ 309 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 310 /* 311 * The I2C EEPROM on the TAM3517 contains 312 * mac address and production data 313 */ 314 struct tam3517_module_info { 315 char customer[48]; 316 char product[48]; 317 318 /* 319 * bit 0~47 : sequence number 320 * bit 48~55 : week of year, from 0. 321 * bit 56~63 : year 322 */ 323 unsigned long long sequence_number; 324 325 /* 326 * bit 0~7 : revision fixed 327 * bit 8~15 : revision major 328 * bit 16~31 : TNxxx 329 */ 330 unsigned int revision; 331 unsigned char eth_addr[4][8]; 332 unsigned char _rev[100]; 333 }; 334 335 #define TAM3517_READ_EEPROM(info, ret) \ 336 do { \ 337 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 338 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 339 (void *)info, sizeof(*info))) \ 340 ret = 1; \ 341 else \ 342 ret = 0; \ 343 } while (0) 344 345 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 346 do { \ 347 char buf[80], ethname[20]; \ 348 int i; \ 349 memset(buf, 0, sizeof(buf)); \ 350 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 351 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 352 (info)->eth_addr[i][5], \ 353 (info)->eth_addr[i][4], \ 354 (info)->eth_addr[i][3], \ 355 (info)->eth_addr[i][2], \ 356 (info)->eth_addr[i][1], \ 357 (info)->eth_addr[i][0]); \ 358 \ 359 if (i) \ 360 sprintf(ethname, "eth%daddr", i); \ 361 else \ 362 strcpy(ethname, "ethaddr"); \ 363 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 364 setenv(ethname, buf); \ 365 } \ 366 } while (0) 367 368 /* The following macros are taken from Technexion's documentation */ 369 #define TAM3517_sequence_number(info) \ 370 ((info)->sequence_number % 0x1000000000000LL) 371 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 372 #define TAM3517_year(info) ((info)->sequence_number >> 56) 373 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 374 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 375 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 376 377 #define TAM3517_PRINT_SOM_INFO(info) \ 378 do { \ 379 printf("Vendor:%s\n", (info)->customer); \ 380 printf("SOM: %s\n", (info)->product); \ 381 printf("SeqNr: %02llu%02llu%012llu\n", \ 382 TAM3517_year(info), \ 383 TAM3517_week_of_year(info), \ 384 TAM3517_sequence_number(info)); \ 385 printf("Rev: TN%u %u.%u\n", \ 386 TAM3517_revision_tn(info), \ 387 TAM3517_revision_major(info), \ 388 TAM3517_revision_fixed(info)); \ 389 } while (0) 390 391 #endif 392 393 #endif /* __TAM3517_H */ 394