1 /*
2  * Copyright (C) 2011
3  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4  *
5  * Copyright (C) 2009 TechNexion Ltd.
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __TAM3517_H
11 #define __TAM3517_H
12 
13 /*
14  * High Level Configuration Options
15  */
16 #define CONFIG_OMAP		/* in a TI OMAP core */
17 #define CONFIG_OMAP_GPIO
18 /* Common ARM Erratas */
19 #define CONFIG_ARM_ERRATA_454179
20 #define CONFIG_ARM_ERRATA_430973
21 #define CONFIG_ARM_ERRATA_621766
22 
23 #define CONFIG_SYS_TEXT_BASE 0x80008000
24 
25 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
26 
27 #include <asm/arch/cpu.h>		/* get chip and board defs */
28 #include <asm/arch/omap.h>
29 
30 /* Clock Defines */
31 #define V_OSCK			26000000	/* Clock output from T2 */
32 #define V_SCLK			(V_OSCK >> 1)
33 
34 #define CONFIG_MISC_INIT_R
35 
36 #define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
37 #define CONFIG_SETUP_MEMORY_TAGS
38 #define CONFIG_INITRD_TAG
39 #define CONFIG_REVISION_TAG
40 
41 /*
42  * Size of malloc() pool
43  */
44 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
45 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
46 					2 * 1024 * 1024)
47 /*
48  * DDR related
49  */
50 #define CONFIG_OMAP3_MICRON_DDR		/* Micron DDR */
51 #define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
52 
53 /*
54  * Hardware drivers
55  */
56 
57 /*
58  * NS16550 Configuration
59  */
60 #define CONFIG_SYS_NS16550_SERIAL
61 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
62 #define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */
63 
64 /*
65  * select serial console configuration
66  */
67 #define CONFIG_CONS_INDEX		1
68 #define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
69 #define CONFIG_SERIAL1			/* UART1 */
70 
71 /* allow to overwrite serial and ethaddr */
72 #define CONFIG_ENV_OVERWRITE
73 #define CONFIG_BAUDRATE			115200
74 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
75 					115200}
76 #define CONFIG_MMC
77 #define CONFIG_OMAP_HSMMC
78 #define CONFIG_GENERIC_MMC
79 #define CONFIG_DOS_PARTITION
80 
81 /* EHCI */
82 #define CONFIG_OMAP3_GPIO_5
83 #define CONFIG_USB_EHCI
84 #define CONFIG_USB_EHCI_OMAP
85 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	25
86 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
87 
88 /* commands to include */
89 #define CONFIG_CMD_NAND		/* NAND support			*/
90 #define CONFIG_CMD_EEPROM
91 
92 #define CONFIG_SYS_NO_FLASH
93 #define CONFIG_SYS_I2C
94 #define CONFIG_SYS_OMAP24_I2C_SPEED	400000
95 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
96 #define CONFIG_SYS_I2C_OMAP34XX
97 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
98 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
99 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
100 
101 /*
102  * Board NAND Info.
103  */
104 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
105 							/* to access */
106 							/* nand at CS0 */
107 
108 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
109 							/* NAND devices */
110 
111 #define CONFIG_AUTO_COMPLETE
112 
113 /*
114  * Miscellaneous configurable options
115  */
116 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
117 #define CONFIG_CMDLINE_EDITING
118 #define CONFIG_AUTO_COMPLETE
119 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
120 
121 /* Print Buffer Size */
122 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
123 					sizeof(CONFIG_SYS_PROMPT) + 16)
124 #define CONFIG_SYS_MAXARGS		32	/* max number of command */
125 						/* args */
126 /* Boot Argument Buffer Size */
127 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
128 /* memtest works on */
129 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
130 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
131 					0x01F00000) /* 31MB */
132 
133 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
134 								/* address */
135 
136 /*
137  * AM3517 has 12 GP timers, they can be driven by the system clock
138  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
139  * This rate is divided by a local divisor.
140  */
141 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
142 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
143 
144 /*
145  * Physical Memory Map
146  */
147 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
148 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
149 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
150 
151 /*
152  * FLASH and environment organization
153  */
154 
155 /* **** PISMO SUPPORT *** */
156 #define CONFIG_NAND
157 #define CONFIG_NAND_OMAP_GPMC
158 #define CONFIG_ENV_IS_IN_NAND
159 #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
160 
161 /* Redundant Environment */
162 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
163 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
164 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
165 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
166 						2 * CONFIG_SYS_ENV_SECT_SIZE)
167 #define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
168 
169 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
170 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
171 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
172 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
173 					 CONFIG_SYS_INIT_RAM_SIZE - \
174 					 GENERATED_GBL_DATA_SIZE)
175 
176 /*
177  * ethernet support, EMAC
178  *
179  */
180 #define CONFIG_DRIVER_TI_EMAC
181 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
182 #define CONFIG_MII
183 #define CONFIG_EMAC_MDIO_PHY_NUM	0
184 #define CONFIG_BOOTP_DNS
185 #define CONFIG_BOOTP_DNS2
186 #define CONFIG_BOOTP_SEND_HOSTNAME
187 #define CONFIG_NET_RETRY_COUNT 10
188 
189 /* Defines for SPL */
190 #define CONFIG_SPL_FRAMEWORK
191 #define CONFIG_SPL_BOARD_INIT
192 #define CONFIG_SPL_CONSOLE
193 #define CONFIG_SPL_NAND_SIMPLE
194 #define CONFIG_SPL_NAND_SOFTECC
195 #define CONFIG_SPL_NAND_WORKSPACE	0x8f07f000 /* below BSS */
196 
197 #define CONFIG_SPL_NAND_BASE
198 #define CONFIG_SPL_NAND_DRIVERS
199 #define CONFIG_SPL_NAND_ECC
200 #define CONFIG_SPL_LDSCRIPT		"arch/arm/mach-omap2/u-boot-spl.lds"
201 
202 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
203 #define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
204 					 CONFIG_SPL_TEXT_BASE)
205 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
206 
207 #define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
208 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
209 #define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
210 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
211 
212 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
213 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
214 
215 /* FAT */
216 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
217 #define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"
218 
219 /* RAW SD card / eMMC */
220 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
221 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
222 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
223 
224 /* NAND boot config */
225 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
226 #define CONFIG_SYS_NAND_PAGE_COUNT	64
227 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
228 #define CONFIG_SYS_NAND_OOBSIZE		64
229 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
230 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
231 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
232 #define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
233 					 48, 49, 50, 51, 52, 53, 54, 55,\
234 					 56, 57, 58, 59, 60, 61, 62, 63}
235 #define CONFIG_SYS_NAND_ECCSIZE		256
236 #define CONFIG_SYS_NAND_ECCBYTES	3
237 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
238 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
239 
240 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
241 
242 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
243 #define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
244 
245 #define CONFIG_CMD_UBIFS
246 #define CONFIG_RBTREE
247 #define CONFIG_LZO
248 #define CONFIG_MTD_PARTITIONS
249 #define CONFIG_MTD_DEVICE
250 #define CONFIG_CMD_MTDPARTS
251 
252 /* Setup MTD for NAND on the SOM */
253 #define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
254 #define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO)," \
255 				"1m(u-boot),256k(env1)," \
256 				"256k(env2),6m(kernel),-(rootfs)"
257 
258 #define	CONFIG_TAM3517_SETTINGS						\
259 	"netdev=eth0\0"							\
260 	"nandargs=setenv bootargs root=${nandroot} "			\
261 		"rootfstype=${nandrootfstype}\0"			\
262 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
263 		"nfsroot=${serverip}:${rootpath}\0"			\
264 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
265 	"addip_sta=setenv bootargs ${bootargs} "			\
266 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
267 		":${hostname}:${netdev}:off panic=1\0"			\
268 	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
269 	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
270 		"else run addip_sta;fi\0"				\
271 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
272 	"addtty=setenv bootargs ${bootargs}"				\
273 		" console=ttyO0,${baudrate}\0"				\
274 	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
275 	"loadaddr=82000000\0"						\
276 	"kernel_addr_r=82000000\0"					\
277 	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
278 	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
279 	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
280 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
281 	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
282 		"bootm ${kernel_addr}\0"				\
283 	"nandboot=run nandargs addip addtty addmtd addmisc;"		\
284 		"nand read ${kernel_addr_r} kernel\0"			\
285 		"bootm ${kernel_addr_r}\0"				\
286 	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
287 		"run nfsargs addip addtty addmtd addmisc;"		\
288 		"bootm ${kernel_addr_r}\0"				\
289 	"net_self=if run net_self_load;then "				\
290 		"run ramargs addip addtty addmtd addmisc;"		\
291 		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
292 		"else echo Images not loades;fi\0"			\
293 	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
294 	"load=tftp ${loadaddr} ${u-boot}\0"				\
295 	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
296 	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
297 	"uboot_addr=0x80000\0"						\
298 	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
299 		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
300 	"updatemlo=nandecc hw;nand erase 0 20000;"			\
301 		"nand write ${loadaddr} 0 20000\0"			\
302 	"upd=if run load;then echo Updating u-boot;if run update;"	\
303 		"then echo U-Boot updated;"				\
304 			"else echo Error updating u-boot !;"		\
305 			"echo Board without bootloader !!;"		\
306 		"fi;"							\
307 		"else echo U-Boot not downloaded..exiting;fi\0"		\
308 
309 /*
310  * this is common code for all TAM3517 boards.
311  * MAC address is stored from manufacturer in
312  * I2C EEPROM
313  */
314 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
315 /*
316  * The I2C EEPROM on the TAM3517 contains
317  * mac address and production data
318  */
319 struct tam3517_module_info {
320 	char customer[48];
321 	char product[48];
322 
323 	/*
324 	 * bit 0~47  : sequence number
325 	 * bit 48~55 : week of year, from 0.
326 	 * bit 56~63 : year
327 	 */
328 	unsigned long long sequence_number;
329 
330 	/*
331 	 * bit 0~7   : revision fixed
332 	 * bit 8~15  : revision major
333 	 * bit 16~31 : TNxxx
334 	 */
335 	unsigned int revision;
336 	unsigned char eth_addr[4][8];
337 	unsigned char _rev[100];
338 };
339 
340 #define TAM3517_READ_EEPROM(info, ret) \
341 do {								\
342 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
343 	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,		\
344 		(void *)info, sizeof(*info)))			\
345 		ret = 1;					\
346 	else							\
347 		ret = 0;					\
348 } while (0)
349 
350 #define TAM3517_READ_MAC_FROM_EEPROM(info)			\
351 do {								\
352 	char buf[80], ethname[20];				\
353 	int i;							\
354 	memset(buf, 0, sizeof(buf));				\
355 	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) {	\
356 		sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X",	\
357 			(info)->eth_addr[i][5],			\
358 			(info)->eth_addr[i][4],			\
359 			(info)->eth_addr[i][3],			\
360 			(info)->eth_addr[i][2],			\
361 			(info)->eth_addr[i][1],			\
362 			(info)->eth_addr[i][0]);			\
363 								\
364 		if (i)						\
365 			sprintf(ethname, "eth%daddr", i);	\
366 		else						\
367 			strcpy(ethname, "ethaddr");		\
368 		printf("Setting %s from EEPROM with %s\n", ethname, buf);\
369 		setenv(ethname, buf);				\
370 	}							\
371 } while (0)
372 
373 /* The following macros are taken from Technexion's documentation */
374 #define TAM3517_sequence_number(info) \
375 	((info)->sequence_number % 0x1000000000000LL)
376 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
377 #define TAM3517_year(info) ((info)->sequence_number >> 56)
378 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
379 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
380 #define TAM3517_revision_tn(info) ((info)->revision >> 16)
381 
382 #define TAM3517_PRINT_SOM_INFO(info)				\
383 do {								\
384 	printf("Vendor:%s\n", (info)->customer);		\
385 	printf("SOM:   %s\n", (info)->product);			\
386 	printf("SeqNr: %02llu%02llu%012llu\n",			\
387 		TAM3517_year(info),				\
388 		TAM3517_week_of_year(info),			\
389 		TAM3517_sequence_number(info));			\
390 	printf("Rev:   TN%u %u.%u\n",				\
391 		TAM3517_revision_tn(info),			\
392 		TAM3517_revision_major(info),			\
393 		TAM3517_revision_fixed(info));			\
394 } while (0)
395 
396 #endif
397 
398 #endif /* __TAM3517_H */
399