1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __TAM3517_H 11 #define __TAM3517_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_OMAP /* in a TI OMAP core */ 17 #define CONFIG_OMAP_GPIO 18 /* Common ARM Erratas */ 19 #define CONFIG_ARM_ERRATA_454179 20 #define CONFIG_ARM_ERRATA_430973 21 #define CONFIG_ARM_ERRATA_621766 22 23 #define CONFIG_SYS_TEXT_BASE 0x80008000 24 25 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 26 27 #include <asm/arch/cpu.h> /* get chip and board defs */ 28 #include <asm/arch/omap.h> 29 30 /* Clock Defines */ 31 #define V_OSCK 26000000 /* Clock output from T2 */ 32 #define V_SCLK (V_OSCK >> 1) 33 34 #define CONFIG_MISC_INIT_R 35 36 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 37 #define CONFIG_SETUP_MEMORY_TAGS 38 #define CONFIG_INITRD_TAG 39 #define CONFIG_REVISION_TAG 40 41 /* 42 * Size of malloc() pool 43 */ 44 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 45 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 46 2 * 1024 * 1024) 47 /* 48 * DDR related 49 */ 50 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ 51 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 52 53 /* 54 * Hardware drivers 55 */ 56 57 /* 58 * NS16550 Configuration 59 */ 60 #define CONFIG_SYS_NS16550_SERIAL 61 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 62 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 63 64 /* 65 * select serial console configuration 66 */ 67 #define CONFIG_CONS_INDEX 1 68 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 69 #define CONFIG_SERIAL1 /* UART1 */ 70 71 /* allow to overwrite serial and ethaddr */ 72 #define CONFIG_ENV_OVERWRITE 73 #define CONFIG_BAUDRATE 115200 74 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 75 115200} 76 #define CONFIG_OMAP_HSMMC 77 #define CONFIG_GENERIC_MMC 78 #define CONFIG_DOS_PARTITION 79 80 /* EHCI */ 81 #define CONFIG_OMAP3_GPIO_5 82 #define CONFIG_USB_EHCI 83 #define CONFIG_USB_EHCI_OMAP 84 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 85 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 86 87 /* commands to include */ 88 #define CONFIG_CMD_NAND /* NAND support */ 89 #define CONFIG_CMD_EEPROM 90 91 #define CONFIG_SYS_NO_FLASH 92 #define CONFIG_SYS_I2C 93 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 94 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 95 #define CONFIG_SYS_I2C_OMAP34XX 96 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 97 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 98 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 99 100 /* 101 * Board NAND Info. 102 */ 103 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 104 /* to access */ 105 /* nand at CS0 */ 106 107 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 108 /* NAND devices */ 109 110 #define CONFIG_AUTO_COMPLETE 111 112 /* 113 * Miscellaneous configurable options 114 */ 115 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 116 #define CONFIG_CMDLINE_EDITING 117 #define CONFIG_AUTO_COMPLETE 118 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 119 120 /* Print Buffer Size */ 121 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 122 sizeof(CONFIG_SYS_PROMPT) + 16) 123 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 124 /* args */ 125 /* Boot Argument Buffer Size */ 126 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 127 /* memtest works on */ 128 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 129 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 130 0x01F00000) /* 31MB */ 131 132 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 133 /* address */ 134 135 /* 136 * AM3517 has 12 GP timers, they can be driven by the system clock 137 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 138 * This rate is divided by a local divisor. 139 */ 140 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 141 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 142 143 /* 144 * Physical Memory Map 145 */ 146 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 147 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 148 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 149 150 /* 151 * FLASH and environment organization 152 */ 153 154 /* **** PISMO SUPPORT *** */ 155 #define CONFIG_NAND 156 #define CONFIG_NAND_OMAP_GPMC 157 #define CONFIG_ENV_IS_IN_NAND 158 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 159 160 /* Redundant Environment */ 161 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 162 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 163 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 164 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 165 2 * CONFIG_SYS_ENV_SECT_SIZE) 166 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 167 168 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 169 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 170 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 171 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 172 CONFIG_SYS_INIT_RAM_SIZE - \ 173 GENERATED_GBL_DATA_SIZE) 174 175 /* 176 * ethernet support, EMAC 177 * 178 */ 179 #define CONFIG_DRIVER_TI_EMAC 180 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 181 #define CONFIG_MII 182 #define CONFIG_EMAC_MDIO_PHY_NUM 0 183 #define CONFIG_BOOTP_DNS 184 #define CONFIG_BOOTP_DNS2 185 #define CONFIG_BOOTP_SEND_HOSTNAME 186 #define CONFIG_NET_RETRY_COUNT 10 187 188 /* Defines for SPL */ 189 #define CONFIG_SPL_FRAMEWORK 190 #define CONFIG_SPL_BOARD_INIT 191 #define CONFIG_SPL_CONSOLE 192 #define CONFIG_SPL_NAND_SIMPLE 193 #define CONFIG_SPL_NAND_SOFTECC 194 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 195 196 #define CONFIG_SPL_NAND_BASE 197 #define CONFIG_SPL_NAND_DRIVERS 198 #define CONFIG_SPL_NAND_ECC 199 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 200 201 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 202 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 203 CONFIG_SPL_TEXT_BASE) 204 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 205 206 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 207 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 208 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 209 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 210 211 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 212 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 213 214 /* FAT */ 215 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 216 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 217 218 /* RAW SD card / eMMC */ 219 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 220 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 221 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 222 223 /* NAND boot config */ 224 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 225 #define CONFIG_SYS_NAND_PAGE_COUNT 64 226 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 227 #define CONFIG_SYS_NAND_OOBSIZE 64 228 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 229 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 230 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 231 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 232 48, 49, 50, 51, 52, 53, 54, 55,\ 233 56, 57, 58, 59, 60, 61, 62, 63} 234 #define CONFIG_SYS_NAND_ECCSIZE 256 235 #define CONFIG_SYS_NAND_ECCBYTES 3 236 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 237 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 238 239 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 240 241 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 242 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 243 244 #define CONFIG_CMD_UBIFS 245 #define CONFIG_RBTREE 246 #define CONFIG_LZO 247 #define CONFIG_MTD_PARTITIONS 248 #define CONFIG_MTD_DEVICE 249 #define CONFIG_CMD_MTDPARTS 250 251 /* Setup MTD for NAND on the SOM */ 252 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 253 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 254 "1m(u-boot),256k(env1)," \ 255 "256k(env2),6m(kernel),-(rootfs)" 256 257 #define CONFIG_TAM3517_SETTINGS \ 258 "netdev=eth0\0" \ 259 "nandargs=setenv bootargs root=${nandroot} " \ 260 "rootfstype=${nandrootfstype}\0" \ 261 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 262 "nfsroot=${serverip}:${rootpath}\0" \ 263 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 264 "addip_sta=setenv bootargs ${bootargs} " \ 265 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 266 ":${hostname}:${netdev}:off panic=1\0" \ 267 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 268 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 269 "else run addip_sta;fi\0" \ 270 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 271 "addtty=setenv bootargs ${bootargs}" \ 272 " console=ttyO0,${baudrate}\0" \ 273 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 274 "loadaddr=82000000\0" \ 275 "kernel_addr_r=82000000\0" \ 276 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 277 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 278 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 279 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 280 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 281 "bootm ${kernel_addr}\0" \ 282 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 283 "nand read ${kernel_addr_r} kernel\0" \ 284 "bootm ${kernel_addr_r}\0" \ 285 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 286 "run nfsargs addip addtty addmtd addmisc;" \ 287 "bootm ${kernel_addr_r}\0" \ 288 "net_self=if run net_self_load;then " \ 289 "run ramargs addip addtty addmtd addmisc;" \ 290 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 291 "else echo Images not loades;fi\0" \ 292 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 293 "load=tftp ${loadaddr} ${u-boot}\0" \ 294 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 295 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 296 "uboot_addr=0x80000\0" \ 297 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 298 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 299 "updatemlo=nandecc hw;nand erase 0 20000;" \ 300 "nand write ${loadaddr} 0 20000\0" \ 301 "upd=if run load;then echo Updating u-boot;if run update;" \ 302 "then echo U-Boot updated;" \ 303 "else echo Error updating u-boot !;" \ 304 "echo Board without bootloader !!;" \ 305 "fi;" \ 306 "else echo U-Boot not downloaded..exiting;fi\0" \ 307 308 /* 309 * this is common code for all TAM3517 boards. 310 * MAC address is stored from manufacturer in 311 * I2C EEPROM 312 */ 313 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 314 /* 315 * The I2C EEPROM on the TAM3517 contains 316 * mac address and production data 317 */ 318 struct tam3517_module_info { 319 char customer[48]; 320 char product[48]; 321 322 /* 323 * bit 0~47 : sequence number 324 * bit 48~55 : week of year, from 0. 325 * bit 56~63 : year 326 */ 327 unsigned long long sequence_number; 328 329 /* 330 * bit 0~7 : revision fixed 331 * bit 8~15 : revision major 332 * bit 16~31 : TNxxx 333 */ 334 unsigned int revision; 335 unsigned char eth_addr[4][8]; 336 unsigned char _rev[100]; 337 }; 338 339 #define TAM3517_READ_EEPROM(info, ret) \ 340 do { \ 341 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 342 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 343 (void *)info, sizeof(*info))) \ 344 ret = 1; \ 345 else \ 346 ret = 0; \ 347 } while (0) 348 349 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 350 do { \ 351 char buf[80], ethname[20]; \ 352 int i; \ 353 memset(buf, 0, sizeof(buf)); \ 354 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 355 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 356 (info)->eth_addr[i][5], \ 357 (info)->eth_addr[i][4], \ 358 (info)->eth_addr[i][3], \ 359 (info)->eth_addr[i][2], \ 360 (info)->eth_addr[i][1], \ 361 (info)->eth_addr[i][0]); \ 362 \ 363 if (i) \ 364 sprintf(ethname, "eth%daddr", i); \ 365 else \ 366 strcpy(ethname, "ethaddr"); \ 367 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 368 setenv(ethname, buf); \ 369 } \ 370 } while (0) 371 372 /* The following macros are taken from Technexion's documentation */ 373 #define TAM3517_sequence_number(info) \ 374 ((info)->sequence_number % 0x1000000000000LL) 375 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 376 #define TAM3517_year(info) ((info)->sequence_number >> 56) 377 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 378 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 379 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 380 381 #define TAM3517_PRINT_SOM_INFO(info) \ 382 do { \ 383 printf("Vendor:%s\n", (info)->customer); \ 384 printf("SOM: %s\n", (info)->product); \ 385 printf("SeqNr: %02llu%02llu%012llu\n", \ 386 TAM3517_year(info), \ 387 TAM3517_week_of_year(info), \ 388 TAM3517_sequence_number(info)); \ 389 printf("Rev: TN%u %u.%u\n", \ 390 TAM3517_revision_tn(info), \ 391 TAM3517_revision_major(info), \ 392 TAM3517_revision_fixed(info)); \ 393 } while (0) 394 395 #endif 396 397 #endif /* __TAM3517_H */ 398