1 /*
2  * Copyright (C) 2011
3  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4  *
5  * Copyright (C) 2009 TechNexion Ltd.
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __TAM3517_H
11 #define __TAM3517_H
12 
13 /*
14  * High Level Configuration Options
15  */
16 #define CONFIG_OMAP		/* in a TI OMAP core */
17 #define CONFIG_OMAP_GPIO
18 
19 #define CONFIG_SYS_TEXT_BASE 0x80008000
20 
21 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
22 
23 #include <asm/arch/cpu.h>		/* get chip and board defs */
24 #include <asm/arch/omap.h>
25 
26 /* Clock Defines */
27 #define V_OSCK			26000000	/* Clock output from T2 */
28 #define V_SCLK			(V_OSCK >> 1)
29 
30 #define CONFIG_MISC_INIT_R
31 
32 #define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
33 #define CONFIG_SETUP_MEMORY_TAGS
34 #define CONFIG_INITRD_TAG
35 #define CONFIG_REVISION_TAG
36 
37 /*
38  * Size of malloc() pool
39  */
40 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
41 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
42 					2 * 1024 * 1024)
43 /*
44  * DDR related
45  */
46 #define CONFIG_OMAP3_MICRON_DDR		/* Micron DDR */
47 #define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
48 
49 /*
50  * Hardware drivers
51  */
52 
53 /*
54  * NS16550 Configuration
55  */
56 #define CONFIG_SYS_NS16550_SERIAL
57 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
58 #define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */
59 
60 /*
61  * select serial console configuration
62  */
63 #define CONFIG_CONS_INDEX		1
64 #define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
65 #define CONFIG_SERIAL1			/* UART1 */
66 
67 /* allow to overwrite serial and ethaddr */
68 #define CONFIG_ENV_OVERWRITE
69 #define CONFIG_BAUDRATE			115200
70 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
71 					115200}
72 /* EHCI */
73 #define CONFIG_OMAP3_GPIO_5
74 #define CONFIG_USB_EHCI
75 #define CONFIG_USB_EHCI_OMAP
76 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	25
77 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
78 
79 /* commands to include */
80 #define CONFIG_CMD_NAND		/* NAND support			*/
81 #define CONFIG_CMD_EEPROM
82 
83 #define CONFIG_SYS_I2C
84 #define CONFIG_SYS_OMAP24_I2C_SPEED	400000
85 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
86 #define CONFIG_SYS_I2C_OMAP34XX
87 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
88 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
89 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
90 
91 /*
92  * Board NAND Info.
93  */
94 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
95 							/* to access */
96 							/* nand at CS0 */
97 
98 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
99 							/* NAND devices */
100 
101 #define CONFIG_AUTO_COMPLETE
102 
103 /*
104  * Miscellaneous configurable options
105  */
106 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
107 #define CONFIG_CMDLINE_EDITING
108 #define CONFIG_AUTO_COMPLETE
109 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
110 
111 /* Print Buffer Size */
112 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
113 					sizeof(CONFIG_SYS_PROMPT) + 16)
114 #define CONFIG_SYS_MAXARGS		32	/* max number of command */
115 						/* args */
116 /* Boot Argument Buffer Size */
117 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
118 /* memtest works on */
119 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
120 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
121 					0x01F00000) /* 31MB */
122 
123 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
124 								/* address */
125 
126 /*
127  * AM3517 has 12 GP timers, they can be driven by the system clock
128  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
129  * This rate is divided by a local divisor.
130  */
131 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
132 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
133 
134 /*
135  * Physical Memory Map
136  */
137 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
138 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
139 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
140 
141 /*
142  * FLASH and environment organization
143  */
144 
145 /* **** PISMO SUPPORT *** */
146 #define CONFIG_NAND
147 #define CONFIG_NAND_OMAP_GPMC
148 #define CONFIG_ENV_IS_IN_NAND
149 #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
150 
151 /* Redundant Environment */
152 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
153 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
154 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
155 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
156 						2 * CONFIG_SYS_ENV_SECT_SIZE)
157 #define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
158 
159 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
160 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
161 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
162 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
163 					 CONFIG_SYS_INIT_RAM_SIZE - \
164 					 GENERATED_GBL_DATA_SIZE)
165 
166 /*
167  * ethernet support, EMAC
168  *
169  */
170 #define CONFIG_DRIVER_TI_EMAC
171 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
172 #define CONFIG_MII
173 #define CONFIG_EMAC_MDIO_PHY_NUM	0
174 #define CONFIG_BOOTP_DNS
175 #define CONFIG_BOOTP_DNS2
176 #define CONFIG_BOOTP_SEND_HOSTNAME
177 #define CONFIG_NET_RETRY_COUNT 10
178 
179 /* Defines for SPL */
180 #define CONFIG_SPL_FRAMEWORK
181 #define CONFIG_SPL_BOARD_INIT
182 #define CONFIG_SPL_CONSOLE
183 #define CONFIG_SPL_NAND_SIMPLE
184 #define CONFIG_SPL_NAND_SOFTECC
185 #define CONFIG_SPL_NAND_WORKSPACE	0x8f07f000 /* below BSS */
186 
187 #define CONFIG_SPL_NAND_BASE
188 #define CONFIG_SPL_NAND_DRIVERS
189 #define CONFIG_SPL_NAND_ECC
190 #define CONFIG_SPL_LDSCRIPT		"arch/arm/mach-omap2/u-boot-spl.lds"
191 
192 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
193 #define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
194 					 CONFIG_SPL_TEXT_BASE)
195 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
196 
197 #define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
198 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
199 #define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
200 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
201 
202 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
203 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
204 
205 /* FAT */
206 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
207 #define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"
208 
209 /* RAW SD card / eMMC */
210 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
211 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
212 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
213 
214 /* NAND boot config */
215 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
216 #define CONFIG_SYS_NAND_PAGE_COUNT	64
217 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
218 #define CONFIG_SYS_NAND_OOBSIZE		64
219 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
220 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
221 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
222 #define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
223 					 48, 49, 50, 51, 52, 53, 54, 55,\
224 					 56, 57, 58, 59, 60, 61, 62, 63}
225 #define CONFIG_SYS_NAND_ECCSIZE		256
226 #define CONFIG_SYS_NAND_ECCBYTES	3
227 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
228 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
229 
230 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
231 
232 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
233 #define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
234 
235 #define CONFIG_CMD_UBIFS
236 #define CONFIG_RBTREE
237 #define CONFIG_LZO
238 #define CONFIG_MTD_PARTITIONS
239 #define CONFIG_MTD_DEVICE
240 #define CONFIG_CMD_MTDPARTS
241 
242 /* Setup MTD for NAND on the SOM */
243 #define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
244 #define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO)," \
245 				"1m(u-boot),256k(env1)," \
246 				"256k(env2),6m(kernel),-(rootfs)"
247 
248 #define	CONFIG_TAM3517_SETTINGS						\
249 	"netdev=eth0\0"							\
250 	"nandargs=setenv bootargs root=${nandroot} "			\
251 		"rootfstype=${nandrootfstype}\0"			\
252 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
253 		"nfsroot=${serverip}:${rootpath}\0"			\
254 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
255 	"addip_sta=setenv bootargs ${bootargs} "			\
256 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
257 		":${hostname}:${netdev}:off panic=1\0"			\
258 	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
259 	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
260 		"else run addip_sta;fi\0"				\
261 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
262 	"addtty=setenv bootargs ${bootargs}"				\
263 		" console=ttyO0,${baudrate}\0"				\
264 	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
265 	"loadaddr=82000000\0"						\
266 	"kernel_addr_r=82000000\0"					\
267 	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
268 	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
269 	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
270 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
271 	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
272 		"bootm ${kernel_addr}\0"				\
273 	"nandboot=run nandargs addip addtty addmtd addmisc;"		\
274 		"nand read ${kernel_addr_r} kernel\0"			\
275 		"bootm ${kernel_addr_r}\0"				\
276 	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
277 		"run nfsargs addip addtty addmtd addmisc;"		\
278 		"bootm ${kernel_addr_r}\0"				\
279 	"net_self=if run net_self_load;then "				\
280 		"run ramargs addip addtty addmtd addmisc;"		\
281 		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
282 		"else echo Images not loades;fi\0"			\
283 	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
284 	"load=tftp ${loadaddr} ${u-boot}\0"				\
285 	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
286 	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
287 	"uboot_addr=0x80000\0"						\
288 	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
289 		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
290 	"updatemlo=nandecc hw;nand erase 0 20000;"			\
291 		"nand write ${loadaddr} 0 20000\0"			\
292 	"upd=if run load;then echo Updating u-boot;if run update;"	\
293 		"then echo U-Boot updated;"				\
294 			"else echo Error updating u-boot !;"		\
295 			"echo Board without bootloader !!;"		\
296 		"fi;"							\
297 		"else echo U-Boot not downloaded..exiting;fi\0"		\
298 
299 /*
300  * this is common code for all TAM3517 boards.
301  * MAC address is stored from manufacturer in
302  * I2C EEPROM
303  */
304 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
305 /*
306  * The I2C EEPROM on the TAM3517 contains
307  * mac address and production data
308  */
309 struct tam3517_module_info {
310 	char customer[48];
311 	char product[48];
312 
313 	/*
314 	 * bit 0~47  : sequence number
315 	 * bit 48~55 : week of year, from 0.
316 	 * bit 56~63 : year
317 	 */
318 	unsigned long long sequence_number;
319 
320 	/*
321 	 * bit 0~7   : revision fixed
322 	 * bit 8~15  : revision major
323 	 * bit 16~31 : TNxxx
324 	 */
325 	unsigned int revision;
326 	unsigned char eth_addr[4][8];
327 	unsigned char _rev[100];
328 };
329 
330 #define TAM3517_READ_EEPROM(info, ret) \
331 do {								\
332 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
333 	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,		\
334 		(void *)info, sizeof(*info)))			\
335 		ret = 1;					\
336 	else							\
337 		ret = 0;					\
338 } while (0)
339 
340 #define TAM3517_READ_MAC_FROM_EEPROM(info)			\
341 do {								\
342 	char buf[80], ethname[20];				\
343 	int i;							\
344 	memset(buf, 0, sizeof(buf));				\
345 	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) {	\
346 		sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X",	\
347 			(info)->eth_addr[i][5],			\
348 			(info)->eth_addr[i][4],			\
349 			(info)->eth_addr[i][3],			\
350 			(info)->eth_addr[i][2],			\
351 			(info)->eth_addr[i][1],			\
352 			(info)->eth_addr[i][0]);			\
353 								\
354 		if (i)						\
355 			sprintf(ethname, "eth%daddr", i);	\
356 		else						\
357 			strcpy(ethname, "ethaddr");		\
358 		printf("Setting %s from EEPROM with %s\n", ethname, buf);\
359 		setenv(ethname, buf);				\
360 	}							\
361 } while (0)
362 
363 /* The following macros are taken from Technexion's documentation */
364 #define TAM3517_sequence_number(info) \
365 	((info)->sequence_number % 0x1000000000000LL)
366 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
367 #define TAM3517_year(info) ((info)->sequence_number >> 56)
368 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
369 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
370 #define TAM3517_revision_tn(info) ((info)->revision >> 16)
371 
372 #define TAM3517_PRINT_SOM_INFO(info)				\
373 do {								\
374 	printf("Vendor:%s\n", (info)->customer);		\
375 	printf("SOM:   %s\n", (info)->product);			\
376 	printf("SeqNr: %02llu%02llu%012llu\n",			\
377 		TAM3517_year(info),				\
378 		TAM3517_week_of_year(info),			\
379 		TAM3517_sequence_number(info));			\
380 	printf("Rev:   TN%u %u.%u\n",				\
381 		TAM3517_revision_tn(info),			\
382 		TAM3517_revision_major(info),			\
383 		TAM3517_revision_fixed(info));			\
384 } while (0)
385 
386 #endif
387 
388 #endif /* __TAM3517_H */
389