1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __TAM3517_H 11 #define __TAM3517_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 17 #define CONFIG_SYS_TEXT_BASE 0x80008000 18 19 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 20 21 #include <asm/arch/cpu.h> /* get chip and board defs */ 22 #include <asm/arch/omap.h> 23 24 /* Clock Defines */ 25 #define V_OSCK 26000000 /* Clock output from T2 */ 26 #define V_SCLK (V_OSCK >> 1) 27 28 #define CONFIG_MISC_INIT_R 29 30 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 31 #define CONFIG_SETUP_MEMORY_TAGS 32 #define CONFIG_INITRD_TAG 33 #define CONFIG_REVISION_TAG 34 35 /* 36 * Size of malloc() pool 37 */ 38 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 39 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 40 2 * 1024 * 1024) 41 /* 42 * DDR related 43 */ 44 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 45 46 /* 47 * Hardware drivers 48 */ 49 50 /* 51 * NS16550 Configuration 52 */ 53 #define CONFIG_SYS_NS16550_SERIAL 54 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 55 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 56 57 /* 58 * select serial console configuration 59 */ 60 #define CONFIG_CONS_INDEX 1 61 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 62 #define CONFIG_SERIAL1 /* UART1 */ 63 64 /* allow to overwrite serial and ethaddr */ 65 #define CONFIG_ENV_OVERWRITE 66 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 67 115200} 68 /* EHCI */ 69 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 70 71 /* commands to include */ 72 #define CONFIG_CMD_NAND /* NAND support */ 73 74 #define CONFIG_SYS_I2C 75 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 76 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 77 #define CONFIG_SYS_I2C_OMAP34XX 78 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 79 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 80 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 81 82 /* 83 * Board NAND Info. 84 */ 85 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 86 /* to access */ 87 /* nand at CS0 */ 88 89 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 90 /* NAND devices */ 91 92 #define CONFIG_AUTO_COMPLETE 93 94 /* 95 * Miscellaneous configurable options 96 */ 97 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 98 #define CONFIG_CMDLINE_EDITING 99 #define CONFIG_AUTO_COMPLETE 100 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 101 102 /* Print Buffer Size */ 103 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 104 sizeof(CONFIG_SYS_PROMPT) + 16) 105 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 106 /* args */ 107 /* Boot Argument Buffer Size */ 108 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 109 /* memtest works on */ 110 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 111 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 112 0x01F00000) /* 31MB */ 113 114 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 115 /* address */ 116 117 /* 118 * AM3517 has 12 GP timers, they can be driven by the system clock 119 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 120 * This rate is divided by a local divisor. 121 */ 122 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 123 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 124 125 /* 126 * Physical Memory Map 127 */ 128 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 129 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 130 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 131 132 /* 133 * FLASH and environment organization 134 */ 135 136 /* **** PISMO SUPPORT *** */ 137 #define CONFIG_NAND 138 #define CONFIG_NAND_OMAP_GPMC 139 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 140 141 /* Redundant Environment */ 142 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 143 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 144 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 145 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 146 2 * CONFIG_SYS_ENV_SECT_SIZE) 147 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 148 149 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 150 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 151 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 152 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 153 CONFIG_SYS_INIT_RAM_SIZE - \ 154 GENERATED_GBL_DATA_SIZE) 155 156 /* 157 * ethernet support, EMAC 158 * 159 */ 160 #define CONFIG_DRIVER_TI_EMAC 161 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 162 #define CONFIG_MII 163 #define CONFIG_BOOTP_DNS 164 #define CONFIG_BOOTP_DNS2 165 #define CONFIG_BOOTP_SEND_HOSTNAME 166 #define CONFIG_NET_RETRY_COUNT 10 167 168 /* Defines for SPL */ 169 #define CONFIG_SPL_FRAMEWORK 170 #define CONFIG_SPL_CONSOLE 171 #define CONFIG_SPL_NAND_SIMPLE 172 #define CONFIG_SPL_NAND_SOFTECC 173 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 174 175 #define CONFIG_SPL_NAND_BASE 176 #define CONFIG_SPL_NAND_DRIVERS 177 #define CONFIG_SPL_NAND_ECC 178 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 179 180 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 181 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 182 CONFIG_SPL_TEXT_BASE) 183 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 184 185 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 186 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 187 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 188 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 189 190 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 191 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 192 193 /* FAT */ 194 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 195 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 196 197 /* RAW SD card / eMMC */ 198 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 199 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 200 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 201 202 /* NAND boot config */ 203 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 204 #define CONFIG_SYS_NAND_PAGE_COUNT 64 205 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 206 #define CONFIG_SYS_NAND_OOBSIZE 64 207 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 208 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 209 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 210 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 211 48, 49, 50, 51, 52, 53, 54, 55,\ 212 56, 57, 58, 59, 60, 61, 62, 63} 213 #define CONFIG_SYS_NAND_ECCSIZE 256 214 #define CONFIG_SYS_NAND_ECCBYTES 3 215 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 216 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 217 218 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 219 220 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 221 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 222 223 #define CONFIG_MTD_PARTITIONS 224 #define CONFIG_MTD_DEVICE 225 226 /* Setup MTD for NAND on the SOM */ 227 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 228 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 229 "1m(u-boot),256k(env1)," \ 230 "256k(env2),6m(kernel),-(rootfs)" 231 232 #define CONFIG_TAM3517_SETTINGS \ 233 "netdev=eth0\0" \ 234 "nandargs=setenv bootargs root=${nandroot} " \ 235 "rootfstype=${nandrootfstype}\0" \ 236 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 237 "nfsroot=${serverip}:${rootpath}\0" \ 238 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 239 "addip_sta=setenv bootargs ${bootargs} " \ 240 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 241 ":${hostname}:${netdev}:off panic=1\0" \ 242 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 243 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 244 "else run addip_sta;fi\0" \ 245 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 246 "addtty=setenv bootargs ${bootargs}" \ 247 " console=ttyO0,${baudrate}\0" \ 248 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 249 "loadaddr=82000000\0" \ 250 "kernel_addr_r=82000000\0" \ 251 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 252 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 253 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 254 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 255 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 256 "bootm ${kernel_addr}\0" \ 257 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 258 "nand read ${kernel_addr_r} kernel\0" \ 259 "bootm ${kernel_addr_r}\0" \ 260 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 261 "run nfsargs addip addtty addmtd addmisc;" \ 262 "bootm ${kernel_addr_r}\0" \ 263 "net_self=if run net_self_load;then " \ 264 "run ramargs addip addtty addmtd addmisc;" \ 265 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 266 "else echo Images not loades;fi\0" \ 267 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 268 "load=tftp ${loadaddr} ${u-boot}\0" \ 269 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 270 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 271 "uboot_addr=0x80000\0" \ 272 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 273 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 274 "updatemlo=nandecc hw;nand erase 0 20000;" \ 275 "nand write ${loadaddr} 0 20000\0" \ 276 "upd=if run load;then echo Updating u-boot;if run update;" \ 277 "then echo U-Boot updated;" \ 278 "else echo Error updating u-boot !;" \ 279 "echo Board without bootloader !!;" \ 280 "fi;" \ 281 "else echo U-Boot not downloaded..exiting;fi\0" \ 282 283 /* 284 * this is common code for all TAM3517 boards. 285 * MAC address is stored from manufacturer in 286 * I2C EEPROM 287 */ 288 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 289 /* 290 * The I2C EEPROM on the TAM3517 contains 291 * mac address and production data 292 */ 293 struct tam3517_module_info { 294 char customer[48]; 295 char product[48]; 296 297 /* 298 * bit 0~47 : sequence number 299 * bit 48~55 : week of year, from 0. 300 * bit 56~63 : year 301 */ 302 unsigned long long sequence_number; 303 304 /* 305 * bit 0~7 : revision fixed 306 * bit 8~15 : revision major 307 * bit 16~31 : TNxxx 308 */ 309 unsigned int revision; 310 unsigned char eth_addr[4][8]; 311 unsigned char _rev[100]; 312 }; 313 314 #define TAM3517_READ_EEPROM(info, ret) \ 315 do { \ 316 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 317 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 318 (void *)info, sizeof(*info))) \ 319 ret = 1; \ 320 else \ 321 ret = 0; \ 322 } while (0) 323 324 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 325 do { \ 326 char buf[80], ethname[20]; \ 327 int i; \ 328 memset(buf, 0, sizeof(buf)); \ 329 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 330 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 331 (info)->eth_addr[i][5], \ 332 (info)->eth_addr[i][4], \ 333 (info)->eth_addr[i][3], \ 334 (info)->eth_addr[i][2], \ 335 (info)->eth_addr[i][1], \ 336 (info)->eth_addr[i][0]); \ 337 \ 338 if (i) \ 339 sprintf(ethname, "eth%daddr", i); \ 340 else \ 341 strcpy(ethname, "ethaddr"); \ 342 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 343 setenv(ethname, buf); \ 344 } \ 345 } while (0) 346 347 /* The following macros are taken from Technexion's documentation */ 348 #define TAM3517_sequence_number(info) \ 349 ((info)->sequence_number % 0x1000000000000LL) 350 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 351 #define TAM3517_year(info) ((info)->sequence_number >> 56) 352 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 353 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 354 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 355 356 #define TAM3517_PRINT_SOM_INFO(info) \ 357 do { \ 358 printf("Vendor:%s\n", (info)->customer); \ 359 printf("SOM: %s\n", (info)->product); \ 360 printf("SeqNr: %02llu%02llu%012llu\n", \ 361 TAM3517_year(info), \ 362 TAM3517_week_of_year(info), \ 363 TAM3517_sequence_number(info)); \ 364 printf("Rev: TN%u %u.%u\n", \ 365 TAM3517_revision_tn(info), \ 366 TAM3517_revision_major(info), \ 367 TAM3517_revision_fixed(info)); \ 368 } while (0) 369 370 #endif 371 372 #endif /* __TAM3517_H */ 373