1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __TAM3517_H 11 #define __TAM3517_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_OMAP /* in a TI OMAP core */ 17 #define CONFIG_OMAP_GPIO 18 /* Common ARM Erratas */ 19 #define CONFIG_ARM_ERRATA_454179 20 #define CONFIG_ARM_ERRATA_430973 21 #define CONFIG_ARM_ERRATA_621766 22 23 #define CONFIG_SYS_TEXT_BASE 0x80008000 24 25 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 26 27 #include <asm/arch/cpu.h> /* get chip and board defs */ 28 #include <asm/arch/omap.h> 29 30 /* Clock Defines */ 31 #define V_OSCK 26000000 /* Clock output from T2 */ 32 #define V_SCLK (V_OSCK >> 1) 33 34 #define CONFIG_MISC_INIT_R 35 36 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 37 #define CONFIG_SETUP_MEMORY_TAGS 38 #define CONFIG_INITRD_TAG 39 #define CONFIG_REVISION_TAG 40 41 /* 42 * Size of malloc() pool 43 */ 44 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 45 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 46 2 * 1024 * 1024) 47 /* 48 * DDR related 49 */ 50 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ 51 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 52 53 /* 54 * Hardware drivers 55 */ 56 57 /* 58 * NS16550 Configuration 59 */ 60 #define CONFIG_SYS_NS16550_SERIAL 61 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 62 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 63 64 /* 65 * select serial console configuration 66 */ 67 #define CONFIG_CONS_INDEX 1 68 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 69 #define CONFIG_SERIAL1 /* UART1 */ 70 71 /* allow to overwrite serial and ethaddr */ 72 #define CONFIG_ENV_OVERWRITE 73 #define CONFIG_BAUDRATE 115200 74 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 75 115200} 76 /* EHCI */ 77 #define CONFIG_OMAP3_GPIO_5 78 #define CONFIG_USB_EHCI 79 #define CONFIG_USB_EHCI_OMAP 80 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 81 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 82 83 /* commands to include */ 84 #define CONFIG_CMD_NAND /* NAND support */ 85 #define CONFIG_CMD_EEPROM 86 87 #define CONFIG_SYS_I2C 88 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 89 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 90 #define CONFIG_SYS_I2C_OMAP34XX 91 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 92 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 93 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 94 95 /* 96 * Board NAND Info. 97 */ 98 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 99 /* to access */ 100 /* nand at CS0 */ 101 102 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 103 /* NAND devices */ 104 105 #define CONFIG_AUTO_COMPLETE 106 107 /* 108 * Miscellaneous configurable options 109 */ 110 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 111 #define CONFIG_CMDLINE_EDITING 112 #define CONFIG_AUTO_COMPLETE 113 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 114 115 /* Print Buffer Size */ 116 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 117 sizeof(CONFIG_SYS_PROMPT) + 16) 118 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 119 /* args */ 120 /* Boot Argument Buffer Size */ 121 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 122 /* memtest works on */ 123 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 124 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 125 0x01F00000) /* 31MB */ 126 127 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 128 /* address */ 129 130 /* 131 * AM3517 has 12 GP timers, they can be driven by the system clock 132 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 133 * This rate is divided by a local divisor. 134 */ 135 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 136 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 137 138 /* 139 * Physical Memory Map 140 */ 141 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 142 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 143 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 144 145 /* 146 * FLASH and environment organization 147 */ 148 149 /* **** PISMO SUPPORT *** */ 150 #define CONFIG_NAND 151 #define CONFIG_NAND_OMAP_GPMC 152 #define CONFIG_ENV_IS_IN_NAND 153 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 154 155 /* Redundant Environment */ 156 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 157 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 158 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 159 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 160 2 * CONFIG_SYS_ENV_SECT_SIZE) 161 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 162 163 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 164 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 165 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 166 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 167 CONFIG_SYS_INIT_RAM_SIZE - \ 168 GENERATED_GBL_DATA_SIZE) 169 170 /* 171 * ethernet support, EMAC 172 * 173 */ 174 #define CONFIG_DRIVER_TI_EMAC 175 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 176 #define CONFIG_MII 177 #define CONFIG_EMAC_MDIO_PHY_NUM 0 178 #define CONFIG_BOOTP_DNS 179 #define CONFIG_BOOTP_DNS2 180 #define CONFIG_BOOTP_SEND_HOSTNAME 181 #define CONFIG_NET_RETRY_COUNT 10 182 183 /* Defines for SPL */ 184 #define CONFIG_SPL_FRAMEWORK 185 #define CONFIG_SPL_BOARD_INIT 186 #define CONFIG_SPL_CONSOLE 187 #define CONFIG_SPL_NAND_SIMPLE 188 #define CONFIG_SPL_NAND_SOFTECC 189 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 190 191 #define CONFIG_SPL_NAND_BASE 192 #define CONFIG_SPL_NAND_DRIVERS 193 #define CONFIG_SPL_NAND_ECC 194 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 195 196 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 197 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 198 CONFIG_SPL_TEXT_BASE) 199 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 200 201 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 202 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 203 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 204 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 205 206 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 207 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 208 209 /* FAT */ 210 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 211 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 212 213 /* RAW SD card / eMMC */ 214 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 215 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 216 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 217 218 /* NAND boot config */ 219 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 220 #define CONFIG_SYS_NAND_PAGE_COUNT 64 221 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 222 #define CONFIG_SYS_NAND_OOBSIZE 64 223 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 224 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 225 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 226 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 227 48, 49, 50, 51, 52, 53, 54, 55,\ 228 56, 57, 58, 59, 60, 61, 62, 63} 229 #define CONFIG_SYS_NAND_ECCSIZE 256 230 #define CONFIG_SYS_NAND_ECCBYTES 3 231 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 232 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 233 234 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 235 236 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 237 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 238 239 #define CONFIG_CMD_UBIFS 240 #define CONFIG_RBTREE 241 #define CONFIG_LZO 242 #define CONFIG_MTD_PARTITIONS 243 #define CONFIG_MTD_DEVICE 244 #define CONFIG_CMD_MTDPARTS 245 246 /* Setup MTD for NAND on the SOM */ 247 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 248 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 249 "1m(u-boot),256k(env1)," \ 250 "256k(env2),6m(kernel),-(rootfs)" 251 252 #define CONFIG_TAM3517_SETTINGS \ 253 "netdev=eth0\0" \ 254 "nandargs=setenv bootargs root=${nandroot} " \ 255 "rootfstype=${nandrootfstype}\0" \ 256 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 257 "nfsroot=${serverip}:${rootpath}\0" \ 258 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 259 "addip_sta=setenv bootargs ${bootargs} " \ 260 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 261 ":${hostname}:${netdev}:off panic=1\0" \ 262 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 263 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 264 "else run addip_sta;fi\0" \ 265 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 266 "addtty=setenv bootargs ${bootargs}" \ 267 " console=ttyO0,${baudrate}\0" \ 268 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 269 "loadaddr=82000000\0" \ 270 "kernel_addr_r=82000000\0" \ 271 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 272 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 273 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 274 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 275 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 276 "bootm ${kernel_addr}\0" \ 277 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 278 "nand read ${kernel_addr_r} kernel\0" \ 279 "bootm ${kernel_addr_r}\0" \ 280 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 281 "run nfsargs addip addtty addmtd addmisc;" \ 282 "bootm ${kernel_addr_r}\0" \ 283 "net_self=if run net_self_load;then " \ 284 "run ramargs addip addtty addmtd addmisc;" \ 285 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 286 "else echo Images not loades;fi\0" \ 287 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 288 "load=tftp ${loadaddr} ${u-boot}\0" \ 289 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 290 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 291 "uboot_addr=0x80000\0" \ 292 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 293 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 294 "updatemlo=nandecc hw;nand erase 0 20000;" \ 295 "nand write ${loadaddr} 0 20000\0" \ 296 "upd=if run load;then echo Updating u-boot;if run update;" \ 297 "then echo U-Boot updated;" \ 298 "else echo Error updating u-boot !;" \ 299 "echo Board without bootloader !!;" \ 300 "fi;" \ 301 "else echo U-Boot not downloaded..exiting;fi\0" \ 302 303 /* 304 * this is common code for all TAM3517 boards. 305 * MAC address is stored from manufacturer in 306 * I2C EEPROM 307 */ 308 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 309 /* 310 * The I2C EEPROM on the TAM3517 contains 311 * mac address and production data 312 */ 313 struct tam3517_module_info { 314 char customer[48]; 315 char product[48]; 316 317 /* 318 * bit 0~47 : sequence number 319 * bit 48~55 : week of year, from 0. 320 * bit 56~63 : year 321 */ 322 unsigned long long sequence_number; 323 324 /* 325 * bit 0~7 : revision fixed 326 * bit 8~15 : revision major 327 * bit 16~31 : TNxxx 328 */ 329 unsigned int revision; 330 unsigned char eth_addr[4][8]; 331 unsigned char _rev[100]; 332 }; 333 334 #define TAM3517_READ_EEPROM(info, ret) \ 335 do { \ 336 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 337 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 338 (void *)info, sizeof(*info))) \ 339 ret = 1; \ 340 else \ 341 ret = 0; \ 342 } while (0) 343 344 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 345 do { \ 346 char buf[80], ethname[20]; \ 347 int i; \ 348 memset(buf, 0, sizeof(buf)); \ 349 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 350 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 351 (info)->eth_addr[i][5], \ 352 (info)->eth_addr[i][4], \ 353 (info)->eth_addr[i][3], \ 354 (info)->eth_addr[i][2], \ 355 (info)->eth_addr[i][1], \ 356 (info)->eth_addr[i][0]); \ 357 \ 358 if (i) \ 359 sprintf(ethname, "eth%daddr", i); \ 360 else \ 361 strcpy(ethname, "ethaddr"); \ 362 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 363 setenv(ethname, buf); \ 364 } \ 365 } while (0) 366 367 /* The following macros are taken from Technexion's documentation */ 368 #define TAM3517_sequence_number(info) \ 369 ((info)->sequence_number % 0x1000000000000LL) 370 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 371 #define TAM3517_year(info) ((info)->sequence_number >> 56) 372 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 373 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 374 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 375 376 #define TAM3517_PRINT_SOM_INFO(info) \ 377 do { \ 378 printf("Vendor:%s\n", (info)->customer); \ 379 printf("SOM: %s\n", (info)->product); \ 380 printf("SeqNr: %02llu%02llu%012llu\n", \ 381 TAM3517_year(info), \ 382 TAM3517_week_of_year(info), \ 383 TAM3517_sequence_number(info)); \ 384 printf("Rev: TN%u %u.%u\n", \ 385 TAM3517_revision_tn(info), \ 386 TAM3517_revision_major(info), \ 387 TAM3517_revision_fixed(info)); \ 388 } while (0) 389 390 #endif 391 392 #endif /* __TAM3517_H */ 393