1 /*
2  * Copyright (C) 2011
3  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4  *
5  * Copyright (C) 2009 TechNexion Ltd.
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __TAM3517_H
11 #define __TAM3517_H
12 
13 /*
14  * High Level Configuration Options
15  */
16 #define CONFIG_OMAP		/* in a TI OMAP core */
17 #define CONFIG_OMAP34XX		/* which is a 34XX */
18 #define CONFIG_OMAP_GPIO
19 #define CONFIG_OMAP_COMMON
20 
21 #define CONFIG_SYS_TEXT_BASE 0x80008000
22 
23 #define CONFIG_SYS_CACHELINE_SIZE	64
24 
25 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
26 
27 #include <asm/arch/cpu.h>		/* get chip and board defs */
28 #include <asm/arch/omap3.h>
29 
30 /*
31  * Display CPU and Board information
32  */
33 #define CONFIG_DISPLAY_CPUINFO
34 #define CONFIG_DISPLAY_BOARDINFO
35 
36 /* Clock Defines */
37 #define V_OSCK			26000000	/* Clock output from T2 */
38 #define V_SCLK			(V_OSCK >> 1)
39 
40 #define CONFIG_MISC_INIT_R
41 
42 #define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
43 #define CONFIG_SETUP_MEMORY_TAGS
44 #define CONFIG_INITRD_TAG
45 #define CONFIG_REVISION_TAG
46 
47 /*
48  * Size of malloc() pool
49  */
50 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
51 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
52 					2 * 1024 * 1024)
53 /*
54  * DDR related
55  */
56 #define CONFIG_OMAP3_MICRON_DDR		/* Micron DDR */
57 #define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
58 
59 /*
60  * Hardware drivers
61  */
62 
63 /*
64  * NS16550 Configuration
65  */
66 #define CONFIG_SYS_NS16550
67 #define CONFIG_SYS_NS16550_SERIAL
68 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
69 #define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */
70 
71 /*
72  * select serial console configuration
73  */
74 #define CONFIG_CONS_INDEX		1
75 #define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
76 #define CONFIG_SERIAL1			/* UART1 */
77 
78 /* allow to overwrite serial and ethaddr */
79 #define CONFIG_ENV_OVERWRITE
80 #define CONFIG_BAUDRATE			115200
81 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
82 					115200}
83 #define CONFIG_MMC
84 #define CONFIG_OMAP_HSMMC
85 #define CONFIG_GENERIC_MMC
86 #define CONFIG_DOS_PARTITION
87 
88 /* EHCI */
89 #define CONFIG_OMAP3_GPIO_5
90 #define CONFIG_USB_EHCI
91 #define CONFIG_USB_EHCI_OMAP
92 #define CONFIG_USB_ULPI
93 #define CONFIG_USB_ULPI_VIEWPORT_OMAP
94 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	25
95 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
96 #define CONFIG_USB_STORAGE
97 
98 /* commands to include */
99 #include <config_cmd_default.h>
100 
101 #define CONFIG_CMD_CACHE
102 #define CONFIG_CMD_DHCP
103 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
104 #define CONFIG_CMD_FAT		/* FAT support			*/
105 #define CONFIG_CMD_GPIO
106 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
107 #define CONFIG_CMD_MII
108 #define CONFIG_CMD_MMC		/* MMC support			*/
109 #define CONFIG_CMD_NET
110 #define CONFIG_CMD_NFS
111 #define CONFIG_CMD_NAND		/* NAND support			*/
112 #define CONFIG_CMD_PING
113 #define CONFIG_CMD_USB
114 #define CONFIG_CMD_EEPROM
115 
116 #undef CONFIG_CMD_FLASH		/* only NAND on the SOM */
117 #undef CONFIG_CMD_IMLS
118 
119 #define CONFIG_SYS_NO_FLASH
120 #define CONFIG_HARD_I2C
121 #define CONFIG_SYS_I2C_SPEED		400000
122 #define CONFIG_SYS_I2C_SLAVE		1
123 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
124 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
125 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
126 #define CONFIG_DRIVER_OMAP34XX_I2C
127 
128 
129 /*
130  * Board NAND Info.
131  */
132 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
133 							/* to access */
134 							/* nand at CS0 */
135 
136 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
137 							/* NAND devices */
138 
139 #define CONFIG_AUTO_COMPLETE
140 
141 /*
142  * Miscellaneous configurable options
143  */
144 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
145 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
146 #define CONFIG_CMDLINE_EDITING
147 #define CONFIG_AUTO_COMPLETE
148 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
149 
150 /* Print Buffer Size */
151 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
152 					sizeof(CONFIG_SYS_PROMPT) + 16)
153 #define CONFIG_SYS_MAXARGS		32	/* max number of command */
154 						/* args */
155 /* Boot Argument Buffer Size */
156 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
157 /* memtest works on */
158 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
159 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
160 					0x01F00000) /* 31MB */
161 
162 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
163 								/* address */
164 
165 /*
166  * AM3517 has 12 GP timers, they can be driven by the system clock
167  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
168  * This rate is divided by a local divisor.
169  */
170 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
171 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
172 #define CONFIG_SYS_HZ			1000
173 
174 /*
175  * Physical Memory Map
176  */
177 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
178 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
179 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
180 
181 /*
182  * FLASH and environment organization
183  */
184 
185 /* **** PISMO SUPPORT *** */
186 
187 /* Configure the PISMO */
188 #define PISMO1_NAND_SIZE		GPMC_SIZE_128M
189 
190 #define CONFIG_NAND_OMAP_GPMC
191 #define GPMC_NAND_ECC_LP_x16_LAYOUT
192 #define CONFIG_ENV_IS_IN_NAND
193 #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
194 
195 /* Redundant Environment */
196 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
197 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
198 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
199 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
200 						2 * CONFIG_SYS_ENV_SECT_SIZE)
201 #define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
202 
203 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
204 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
205 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
206 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
207 					 CONFIG_SYS_INIT_RAM_SIZE - \
208 					 GENERATED_GBL_DATA_SIZE)
209 
210 /*
211  * ethernet support, EMAC
212  *
213  */
214 #define CONFIG_DRIVER_TI_EMAC
215 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
216 #define CONFIG_MII
217 #define CONFIG_EMAC_MDIO_PHY_NUM	0
218 #define CONFIG_BOOTP_DNS
219 #define CONFIG_BOOTP_DNS2
220 #define CONFIG_BOOTP_SEND_HOSTNAME
221 #define CONFIG_NET_RETRY_COUNT 10
222 
223 /* Defines for SPL */
224 #define CONFIG_SPL
225 #define CONFIG_SPL_FRAMEWORK
226 #define CONFIG_SPL_BOARD_INIT
227 #define CONFIG_SPL_CONSOLE
228 #define CONFIG_SPL_NAND_SIMPLE
229 #define CONFIG_SPL_NAND_SOFTECC
230 #define CONFIG_SPL_NAND_WORKSPACE	0x8f07f000 /* below BSS */
231 
232 #define CONFIG_SPL_LIBCOMMON_SUPPORT
233 #define CONFIG_SPL_LIBDISK_SUPPORT
234 #define CONFIG_SPL_I2C_SUPPORT
235 #define CONFIG_SPL_LIBGENERIC_SUPPORT
236 #define CONFIG_SPL_SERIAL_SUPPORT
237 #define CONFIG_SPL_GPIO_SUPPORT
238 #define CONFIG_SPL_POWER_SUPPORT
239 #define CONFIG_SPL_NAND_SUPPORT
240 #define CONFIG_SPL_NAND_BASE
241 #define CONFIG_SPL_NAND_DRIVERS
242 #define CONFIG_SPL_NAND_ECC
243 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
244 
245 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
246 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
247 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
248 
249 #define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
250 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
251 #define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
252 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
253 
254 /* NAND boot config */
255 #define CONFIG_SYS_NAND_PAGE_COUNT	64
256 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
257 #define CONFIG_SYS_NAND_OOBSIZE		64
258 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
259 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
260 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
261 #define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
262 					 48, 49, 50, 51, 52, 53, 54, 55,\
263 					 56, 57, 58, 59, 60, 61, 62, 63}
264 #define CONFIG_SYS_NAND_ECCSIZE		256
265 #define CONFIG_SYS_NAND_ECCBYTES	3
266 
267 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
268 
269 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
270 #define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
271 
272 #define CONFIG_OF_LIBFDT
273 #define CONFIG_FIT
274 #define CONFIG_CMD_UBI
275 #define CONFIG_CMD_UBIFS
276 #define CONFIG_RBTREE
277 #define CONFIG_LZO
278 #define CONFIG_MTD_PARTITIONS
279 #define CONFIG_MTD_DEVICE
280 #define CONFIG_CMD_MTDPARTS
281 
282 /* Setup MTD for NAND on the SOM */
283 #define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
284 #define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO)," \
285 				"1m(u-boot),256k(env1)," \
286 				"256k(env2),6m(kernel),-(rootfs)"
287 
288 #define	CONFIG_TAM3517_SETTINGS						\
289 	"netdev=eth0\0"							\
290 	"nandargs=setenv bootargs root=${nandroot} "			\
291 		"rootfstype=${nandrootfstype}\0"			\
292 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
293 		"nfsroot=${serverip}:${rootpath}\0"			\
294 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
295 	"addip_sta=setenv bootargs ${bootargs} "			\
296 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
297 		":${hostname}:${netdev}:off panic=1\0"			\
298 	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
299 	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
300 		"else run addip_sta;fi\0"				\
301 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
302 	"addtty=setenv bootargs ${bootargs}"				\
303 		" console=ttyO0,${baudrate}\0"				\
304 	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
305 	"loadaddr=82000000\0"						\
306 	"kernel_addr_r=82000000\0"					\
307 	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
308 	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
309 	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
310 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
311 	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
312 		"bootm ${kernel_addr}\0"				\
313 	"nandboot=run nandargs addip addtty addmtd addmisc;"		\
314 		"nand read ${kernel_addr_r} kernel\0"			\
315 		"bootm ${kernel_addr_r}\0"				\
316 	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
317 		"run nfsargs addip addtty addmtd addmisc;"		\
318 		"bootm ${kernel_addr_r}\0"				\
319 	"net_self=if run net_self_load;then "				\
320 		"run ramargs addip addtty addmtd addmisc;"		\
321 		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
322 		"else echo Images not loades;fi\0"			\
323 	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
324 	"load=tftp ${loadaddr} ${u-boot}\0"				\
325 	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
326 	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
327 	"uboot_addr=0x80000\0"						\
328 	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
329 		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
330 	"updatemlo=nandecc hw;nand erase 0 20000;"			\
331 		"nand write ${loadaddr} 0 20000\0"			\
332 	"upd=if run load;then echo Updating u-boot;if run update;"	\
333 		"then echo U-Boot updated;"				\
334 			"else echo Error updating u-boot !;"		\
335 			"echo Board without bootloader !!;"		\
336 		"fi;"							\
337 		"else echo U-Boot not downloaded..exiting;fi\0"		\
338 
339 
340 /*
341  * this is common code for all TAM3517 boards.
342  * MAC address is stored from manufacturer in
343  * I2C EEPROM
344  */
345 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
346 /*
347  * The I2C EEPROM on the TAM3517 contains
348  * mac address and production data
349  */
350 struct tam3517_module_info {
351 	char customer[48];
352 	char product[48];
353 
354 	/*
355 	 * bit 0~47  : sequence number
356 	 * bit 48~55 : week of year, from 0.
357 	 * bit 56~63 : year
358 	 */
359 	unsigned long long sequence_number;
360 
361 	/*
362 	 * bit 0~7   : revision fixed
363 	 * bit 8~15  : revision major
364 	 * bit 16~31 : TNxxx
365 	 */
366 	unsigned int revision;
367 	unsigned char eth_addr[4][8];
368 	unsigned char _rev[100];
369 };
370 
371 #define TAM3517_READ_EEPROM(info, ret) \
372 do {								\
373 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);	\
374 	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,		\
375 		(void *)info, sizeof(*info)))			\
376 		ret = 1;					\
377 	else							\
378 		ret = 0;					\
379 } while (0)
380 
381 #define TAM3517_READ_MAC_FROM_EEPROM(info)			\
382 do {								\
383 	char buf[80], ethname[20];				\
384 	int i;							\
385 	memset(buf, 0, sizeof(buf));				\
386 	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) {	\
387 		sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X",	\
388 			(info)->eth_addr[i][5],			\
389 			(info)->eth_addr[i][4],			\
390 			(info)->eth_addr[i][3],			\
391 			(info)->eth_addr[i][2],			\
392 			(info)->eth_addr[i][1],			\
393 			(info)->eth_addr[i][0]);			\
394 								\
395 		if (i)						\
396 			sprintf(ethname, "eth%daddr", i);	\
397 		else						\
398 			sprintf(ethname, "ethaddr");		\
399 		printf("Setting %s from EEPROM with %s\n", ethname, buf);\
400 		setenv(ethname, buf);				\
401 	}							\
402 } while (0)
403 
404 /* The following macros are taken from Technexion's documentation */
405 #define TAM3517_sequence_number(info) \
406 	((info)->sequence_number % 0x1000000000000LL)
407 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
408 #define TAM3517_year(info) ((info)->sequence_number >> 56)
409 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
410 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
411 #define TAM3517_revision_tn(info) ((info)->revision >> 16)
412 
413 #define TAM3517_PRINT_SOM_INFO(info)				\
414 do {								\
415 	printf("Vendor:%s\n", (info)->customer);		\
416 	printf("SOM:   %s\n", (info)->product);			\
417 	printf("SeqNr: %02llu%02llu%012llu\n",			\
418 		TAM3517_year(info),				\
419 		TAM3517_week_of_year(info),			\
420 		TAM3517_sequence_number(info));			\
421 	printf("Rev:   TN%u %u.%u\n",				\
422 		TAM3517_revision_tn(info),			\
423 		TAM3517_revision_major(info),			\
424 		TAM3517_revision_fixed(info));			\
425 } while (0)
426 
427 #endif
428 
429 #endif /* __TAM3517_H */
430