1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __TAM3517_H 11 #define __TAM3517_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 17 #define CONFIG_SYS_TEXT_BASE 0x80008000 18 19 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 20 21 #include <asm/arch/cpu.h> /* get chip and board defs */ 22 #include <asm/arch/omap.h> 23 24 /* Clock Defines */ 25 #define V_OSCK 26000000 /* Clock output from T2 */ 26 #define V_SCLK (V_OSCK >> 1) 27 28 #define CONFIG_MISC_INIT_R 29 30 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 31 #define CONFIG_SETUP_MEMORY_TAGS 32 #define CONFIG_INITRD_TAG 33 #define CONFIG_REVISION_TAG 34 35 /* 36 * Size of malloc() pool 37 */ 38 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 39 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 40 2 * 1024 * 1024) 41 /* 42 * DDR related 43 */ 44 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 45 46 /* 47 * Hardware drivers 48 */ 49 50 /* 51 * NS16550 Configuration 52 */ 53 #define CONFIG_SYS_NS16550_SERIAL 54 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 55 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 56 57 /* 58 * select serial console configuration 59 */ 60 #define CONFIG_CONS_INDEX 1 61 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 62 #define CONFIG_SERIAL1 /* UART1 */ 63 64 /* allow to overwrite serial and ethaddr */ 65 #define CONFIG_ENV_OVERWRITE 66 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 67 115200} 68 /* EHCI */ 69 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 70 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 71 72 /* commands to include */ 73 #define CONFIG_CMD_NAND /* NAND support */ 74 75 #define CONFIG_SYS_I2C 76 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 77 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 78 #define CONFIG_SYS_I2C_OMAP34XX 79 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 80 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 81 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 82 83 /* 84 * Board NAND Info. 85 */ 86 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 87 /* to access */ 88 /* nand at CS0 */ 89 90 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 91 /* NAND devices */ 92 93 #define CONFIG_AUTO_COMPLETE 94 95 /* 96 * Miscellaneous configurable options 97 */ 98 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 99 #define CONFIG_CMDLINE_EDITING 100 #define CONFIG_AUTO_COMPLETE 101 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 102 103 /* Print Buffer Size */ 104 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 105 sizeof(CONFIG_SYS_PROMPT) + 16) 106 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 107 /* args */ 108 /* Boot Argument Buffer Size */ 109 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 110 /* memtest works on */ 111 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 112 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 113 0x01F00000) /* 31MB */ 114 115 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 116 /* address */ 117 118 /* 119 * AM3517 has 12 GP timers, they can be driven by the system clock 120 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 121 * This rate is divided by a local divisor. 122 */ 123 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 124 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 125 126 /* 127 * Physical Memory Map 128 */ 129 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 130 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 131 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 132 133 /* 134 * FLASH and environment organization 135 */ 136 137 /* **** PISMO SUPPORT *** */ 138 #define CONFIG_NAND 139 #define CONFIG_NAND_OMAP_GPMC 140 #define CONFIG_ENV_IS_IN_NAND 141 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 142 143 /* Redundant Environment */ 144 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 145 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 146 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 147 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 148 2 * CONFIG_SYS_ENV_SECT_SIZE) 149 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 150 151 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 152 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 153 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 154 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 155 CONFIG_SYS_INIT_RAM_SIZE - \ 156 GENERATED_GBL_DATA_SIZE) 157 158 /* 159 * ethernet support, EMAC 160 * 161 */ 162 #define CONFIG_DRIVER_TI_EMAC 163 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 164 #define CONFIG_MII 165 #define CONFIG_BOOTP_DNS 166 #define CONFIG_BOOTP_DNS2 167 #define CONFIG_BOOTP_SEND_HOSTNAME 168 #define CONFIG_NET_RETRY_COUNT 10 169 170 /* Defines for SPL */ 171 #define CONFIG_SPL_FRAMEWORK 172 #define CONFIG_SPL_CONSOLE 173 #define CONFIG_SPL_NAND_SIMPLE 174 #define CONFIG_SPL_NAND_SOFTECC 175 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 176 177 #define CONFIG_SPL_NAND_BASE 178 #define CONFIG_SPL_NAND_DRIVERS 179 #define CONFIG_SPL_NAND_ECC 180 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 181 182 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 183 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 184 CONFIG_SPL_TEXT_BASE) 185 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 186 187 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 188 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 189 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 190 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 191 192 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 193 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 194 195 /* FAT */ 196 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 197 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 198 199 /* RAW SD card / eMMC */ 200 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 201 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 202 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 203 204 /* NAND boot config */ 205 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 206 #define CONFIG_SYS_NAND_PAGE_COUNT 64 207 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 208 #define CONFIG_SYS_NAND_OOBSIZE 64 209 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 210 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 211 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 212 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 213 48, 49, 50, 51, 52, 53, 54, 55,\ 214 56, 57, 58, 59, 60, 61, 62, 63} 215 #define CONFIG_SYS_NAND_ECCSIZE 256 216 #define CONFIG_SYS_NAND_ECCBYTES 3 217 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 218 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 219 220 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 221 222 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 223 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 224 225 #define CONFIG_CMD_UBIFS 226 #define CONFIG_RBTREE 227 #define CONFIG_LZO 228 #define CONFIG_MTD_PARTITIONS 229 #define CONFIG_MTD_DEVICE 230 #define CONFIG_CMD_MTDPARTS 231 232 /* Setup MTD for NAND on the SOM */ 233 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 234 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 235 "1m(u-boot),256k(env1)," \ 236 "256k(env2),6m(kernel),-(rootfs)" 237 238 #define CONFIG_TAM3517_SETTINGS \ 239 "netdev=eth0\0" \ 240 "nandargs=setenv bootargs root=${nandroot} " \ 241 "rootfstype=${nandrootfstype}\0" \ 242 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 243 "nfsroot=${serverip}:${rootpath}\0" \ 244 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 245 "addip_sta=setenv bootargs ${bootargs} " \ 246 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 247 ":${hostname}:${netdev}:off panic=1\0" \ 248 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 249 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 250 "else run addip_sta;fi\0" \ 251 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 252 "addtty=setenv bootargs ${bootargs}" \ 253 " console=ttyO0,${baudrate}\0" \ 254 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 255 "loadaddr=82000000\0" \ 256 "kernel_addr_r=82000000\0" \ 257 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 258 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 259 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 260 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 261 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 262 "bootm ${kernel_addr}\0" \ 263 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 264 "nand read ${kernel_addr_r} kernel\0" \ 265 "bootm ${kernel_addr_r}\0" \ 266 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 267 "run nfsargs addip addtty addmtd addmisc;" \ 268 "bootm ${kernel_addr_r}\0" \ 269 "net_self=if run net_self_load;then " \ 270 "run ramargs addip addtty addmtd addmisc;" \ 271 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 272 "else echo Images not loades;fi\0" \ 273 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 274 "load=tftp ${loadaddr} ${u-boot}\0" \ 275 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 276 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 277 "uboot_addr=0x80000\0" \ 278 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 279 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 280 "updatemlo=nandecc hw;nand erase 0 20000;" \ 281 "nand write ${loadaddr} 0 20000\0" \ 282 "upd=if run load;then echo Updating u-boot;if run update;" \ 283 "then echo U-Boot updated;" \ 284 "else echo Error updating u-boot !;" \ 285 "echo Board without bootloader !!;" \ 286 "fi;" \ 287 "else echo U-Boot not downloaded..exiting;fi\0" \ 288 289 /* 290 * this is common code for all TAM3517 boards. 291 * MAC address is stored from manufacturer in 292 * I2C EEPROM 293 */ 294 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 295 /* 296 * The I2C EEPROM on the TAM3517 contains 297 * mac address and production data 298 */ 299 struct tam3517_module_info { 300 char customer[48]; 301 char product[48]; 302 303 /* 304 * bit 0~47 : sequence number 305 * bit 48~55 : week of year, from 0. 306 * bit 56~63 : year 307 */ 308 unsigned long long sequence_number; 309 310 /* 311 * bit 0~7 : revision fixed 312 * bit 8~15 : revision major 313 * bit 16~31 : TNxxx 314 */ 315 unsigned int revision; 316 unsigned char eth_addr[4][8]; 317 unsigned char _rev[100]; 318 }; 319 320 #define TAM3517_READ_EEPROM(info, ret) \ 321 do { \ 322 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 323 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 324 (void *)info, sizeof(*info))) \ 325 ret = 1; \ 326 else \ 327 ret = 0; \ 328 } while (0) 329 330 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 331 do { \ 332 char buf[80], ethname[20]; \ 333 int i; \ 334 memset(buf, 0, sizeof(buf)); \ 335 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 336 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 337 (info)->eth_addr[i][5], \ 338 (info)->eth_addr[i][4], \ 339 (info)->eth_addr[i][3], \ 340 (info)->eth_addr[i][2], \ 341 (info)->eth_addr[i][1], \ 342 (info)->eth_addr[i][0]); \ 343 \ 344 if (i) \ 345 sprintf(ethname, "eth%daddr", i); \ 346 else \ 347 strcpy(ethname, "ethaddr"); \ 348 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 349 setenv(ethname, buf); \ 350 } \ 351 } while (0) 352 353 /* The following macros are taken from Technexion's documentation */ 354 #define TAM3517_sequence_number(info) \ 355 ((info)->sequence_number % 0x1000000000000LL) 356 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 357 #define TAM3517_year(info) ((info)->sequence_number >> 56) 358 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 359 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 360 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 361 362 #define TAM3517_PRINT_SOM_INFO(info) \ 363 do { \ 364 printf("Vendor:%s\n", (info)->customer); \ 365 printf("SOM: %s\n", (info)->product); \ 366 printf("SeqNr: %02llu%02llu%012llu\n", \ 367 TAM3517_year(info), \ 368 TAM3517_week_of_year(info), \ 369 TAM3517_sequence_number(info)); \ 370 printf("Rev: TN%u %u.%u\n", \ 371 TAM3517_revision_tn(info), \ 372 TAM3517_revision_major(info), \ 373 TAM3517_revision_fixed(info)); \ 374 } while (0) 375 376 #endif 377 378 #endif /* __TAM3517_H */ 379