1 /*
2  * Copyright (C) 2011
3  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4  *
5  * Copyright (C) 2009 TechNexion Ltd.
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __TAM3517_H
11 #define __TAM3517_H
12 
13 /*
14  * High Level Configuration Options
15  */
16 
17 #define CONFIG_SYS_TEXT_BASE 0x80008000
18 
19 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
20 
21 #include <asm/arch/cpu.h>		/* get chip and board defs */
22 #include <asm/arch/omap.h>
23 
24 /* Clock Defines */
25 #define V_OSCK			26000000	/* Clock output from T2 */
26 #define V_SCLK			(V_OSCK >> 1)
27 
28 #define CONFIG_MISC_INIT_R
29 
30 #define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
31 #define CONFIG_SETUP_MEMORY_TAGS
32 #define CONFIG_INITRD_TAG
33 #define CONFIG_REVISION_TAG
34 
35 /*
36  * Size of malloc() pool
37  */
38 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
39 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
40 					2 * 1024 * 1024)
41 /*
42  * DDR related
43  */
44 #define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
45 
46 /*
47  * Hardware drivers
48  */
49 
50 /*
51  * NS16550 Configuration
52  */
53 #define CONFIG_SYS_NS16550_SERIAL
54 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
55 #define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */
56 
57 /*
58  * select serial console configuration
59  */
60 #define CONFIG_CONS_INDEX		1
61 #define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
62 #define CONFIG_SERIAL1			/* UART1 */
63 
64 /* allow to overwrite serial and ethaddr */
65 #define CONFIG_ENV_OVERWRITE
66 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
67 					115200}
68 /* EHCI */
69 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	25
70 
71 #define CONFIG_SYS_I2C
72 #define CONFIG_SYS_OMAP24_I2C_SPEED	400000
73 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
74 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
75 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
76 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
77 
78 /*
79  * Board NAND Info.
80  */
81 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
82 							/* to access */
83 							/* nand at CS0 */
84 
85 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
86 							/* NAND devices */
87 
88 #define CONFIG_AUTO_COMPLETE
89 
90 /*
91  * Miscellaneous configurable options
92  */
93 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
94 #define CONFIG_CMDLINE_EDITING
95 #define CONFIG_AUTO_COMPLETE
96 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
97 
98 /* Print Buffer Size */
99 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
100 					sizeof(CONFIG_SYS_PROMPT) + 16)
101 #define CONFIG_SYS_MAXARGS		32	/* max number of command */
102 						/* args */
103 /* Boot Argument Buffer Size */
104 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
105 /* memtest works on */
106 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
107 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
108 					0x01F00000) /* 31MB */
109 
110 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
111 								/* address */
112 
113 /*
114  * AM3517 has 12 GP timers, they can be driven by the system clock
115  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
116  * This rate is divided by a local divisor.
117  */
118 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
119 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
120 
121 /*
122  * Physical Memory Map
123  */
124 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
125 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
126 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
127 
128 /*
129  * FLASH and environment organization
130  */
131 
132 /* **** PISMO SUPPORT *** */
133 #define CONFIG_NAND_OMAP_GPMC
134 #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
135 
136 /* Redundant Environment */
137 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
138 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
139 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
140 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
141 						2 * CONFIG_SYS_ENV_SECT_SIZE)
142 #define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
143 
144 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
145 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
146 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
147 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
148 					 CONFIG_SYS_INIT_RAM_SIZE - \
149 					 GENERATED_GBL_DATA_SIZE)
150 
151 /*
152  * ethernet support, EMAC
153  *
154  */
155 #define CONFIG_DRIVER_TI_EMAC
156 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
157 #define CONFIG_MII
158 #define CONFIG_BOOTP_DNS
159 #define CONFIG_BOOTP_DNS2
160 #define CONFIG_BOOTP_SEND_HOSTNAME
161 #define CONFIG_NET_RETRY_COUNT 10
162 
163 /* Defines for SPL */
164 #define CONFIG_SPL_FRAMEWORK
165 #define CONFIG_SPL_CONSOLE
166 #define CONFIG_SPL_NAND_SIMPLE
167 #define CONFIG_SPL_NAND_SOFTECC
168 #define CONFIG_SPL_NAND_WORKSPACE	0x8f07f000 /* below BSS */
169 
170 #define CONFIG_SPL_NAND_BASE
171 #define CONFIG_SPL_NAND_DRIVERS
172 #define CONFIG_SPL_NAND_ECC
173 #define CONFIG_SPL_LDSCRIPT		"arch/arm/mach-omap2/u-boot-spl.lds"
174 
175 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
176 #define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
177 					 CONFIG_SPL_TEXT_BASE)
178 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
179 
180 #define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
181 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
182 #define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
183 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
184 
185 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
186 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
187 
188 /* FAT */
189 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
190 #define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"
191 
192 /* RAW SD card / eMMC */
193 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
194 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
195 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
196 
197 /* NAND boot config */
198 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
199 #define CONFIG_SYS_NAND_PAGE_COUNT	64
200 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
201 #define CONFIG_SYS_NAND_OOBSIZE		64
202 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
203 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
204 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
205 #define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
206 					 48, 49, 50, 51, 52, 53, 54, 55,\
207 					 56, 57, 58, 59, 60, 61, 62, 63}
208 #define CONFIG_SYS_NAND_ECCSIZE		256
209 #define CONFIG_SYS_NAND_ECCBYTES	3
210 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
211 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
212 
213 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
214 
215 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
216 #define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
217 
218 #define CONFIG_MTD_PARTITIONS
219 #define CONFIG_MTD_DEVICE
220 
221 /* Setup MTD for NAND on the SOM */
222 #define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
223 #define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO)," \
224 				"1m(u-boot),256k(env1)," \
225 				"256k(env2),6m(kernel),-(rootfs)"
226 
227 #define	CONFIG_TAM3517_SETTINGS						\
228 	"netdev=eth0\0"							\
229 	"nandargs=setenv bootargs root=${nandroot} "			\
230 		"rootfstype=${nandrootfstype}\0"			\
231 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
232 		"nfsroot=${serverip}:${rootpath}\0"			\
233 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
234 	"addip_sta=setenv bootargs ${bootargs} "			\
235 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
236 		":${hostname}:${netdev}:off panic=1\0"			\
237 	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
238 	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
239 		"else run addip_sta;fi\0"				\
240 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
241 	"addtty=setenv bootargs ${bootargs}"				\
242 		" console=ttyO0,${baudrate}\0"				\
243 	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
244 	"loadaddr=82000000\0"						\
245 	"kernel_addr_r=82000000\0"					\
246 	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
247 	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
248 	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
249 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
250 	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
251 		"bootm ${kernel_addr}\0"				\
252 	"nandboot=run nandargs addip addtty addmtd addmisc;"		\
253 		"nand read ${kernel_addr_r} kernel\0"			\
254 		"bootm ${kernel_addr_r}\0"				\
255 	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
256 		"run nfsargs addip addtty addmtd addmisc;"		\
257 		"bootm ${kernel_addr_r}\0"				\
258 	"net_self=if run net_self_load;then "				\
259 		"run ramargs addip addtty addmtd addmisc;"		\
260 		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
261 		"else echo Images not loades;fi\0"			\
262 	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
263 	"load=tftp ${loadaddr} ${u-boot}\0"				\
264 	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
265 	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
266 	"uboot_addr=0x80000\0"						\
267 	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
268 		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
269 	"updatemlo=nandecc hw;nand erase 0 20000;"			\
270 		"nand write ${loadaddr} 0 20000\0"			\
271 	"upd=if run load;then echo Updating u-boot;if run update;"	\
272 		"then echo U-Boot updated;"				\
273 			"else echo Error updating u-boot !;"		\
274 			"echo Board without bootloader !!;"		\
275 		"fi;"							\
276 		"else echo U-Boot not downloaded..exiting;fi\0"		\
277 
278 /*
279  * this is common code for all TAM3517 boards.
280  * MAC address is stored from manufacturer in
281  * I2C EEPROM
282  */
283 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
284 /*
285  * The I2C EEPROM on the TAM3517 contains
286  * mac address and production data
287  */
288 struct tam3517_module_info {
289 	char customer[48];
290 	char product[48];
291 
292 	/*
293 	 * bit 0~47  : sequence number
294 	 * bit 48~55 : week of year, from 0.
295 	 * bit 56~63 : year
296 	 */
297 	unsigned long long sequence_number;
298 
299 	/*
300 	 * bit 0~7   : revision fixed
301 	 * bit 8~15  : revision major
302 	 * bit 16~31 : TNxxx
303 	 */
304 	unsigned int revision;
305 	unsigned char eth_addr[4][8];
306 	unsigned char _rev[100];
307 };
308 
309 #define TAM3517_READ_EEPROM(info, ret) \
310 do {								\
311 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
312 	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,		\
313 		(void *)info, sizeof(*info)))			\
314 		ret = 1;					\
315 	else							\
316 		ret = 0;					\
317 } while (0)
318 
319 #define TAM3517_READ_MAC_FROM_EEPROM(info)			\
320 do {								\
321 	char buf[80], ethname[20];				\
322 	int i;							\
323 	memset(buf, 0, sizeof(buf));				\
324 	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) {	\
325 		sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X",	\
326 			(info)->eth_addr[i][5],			\
327 			(info)->eth_addr[i][4],			\
328 			(info)->eth_addr[i][3],			\
329 			(info)->eth_addr[i][2],			\
330 			(info)->eth_addr[i][1],			\
331 			(info)->eth_addr[i][0]);			\
332 								\
333 		if (i)						\
334 			sprintf(ethname, "eth%daddr", i);	\
335 		else						\
336 			strcpy(ethname, "ethaddr");		\
337 		printf("Setting %s from EEPROM with %s\n", ethname, buf);\
338 		setenv(ethname, buf);				\
339 	}							\
340 } while (0)
341 
342 /* The following macros are taken from Technexion's documentation */
343 #define TAM3517_sequence_number(info) \
344 	((info)->sequence_number % 0x1000000000000LL)
345 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
346 #define TAM3517_year(info) ((info)->sequence_number >> 56)
347 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
348 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
349 #define TAM3517_revision_tn(info) ((info)->revision >> 16)
350 
351 #define TAM3517_PRINT_SOM_INFO(info)				\
352 do {								\
353 	printf("Vendor:%s\n", (info)->customer);		\
354 	printf("SOM:   %s\n", (info)->product);			\
355 	printf("SeqNr: %02llu%02llu%012llu\n",			\
356 		TAM3517_year(info),				\
357 		TAM3517_week_of_year(info),			\
358 		TAM3517_sequence_number(info));			\
359 	printf("Rev:   TN%u %u.%u\n",				\
360 		TAM3517_revision_tn(info),			\
361 		TAM3517_revision_major(info),			\
362 		TAM3517_revision_fixed(info));			\
363 } while (0)
364 
365 #endif
366 
367 #endif /* __TAM3517_H */
368