1 /*
2  * Copyright (C) 2011
3  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4  *
5  * Copyright (C) 2009 TechNexion Ltd.
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __TAM3517_H
11 #define __TAM3517_H
12 
13 /*
14  * High Level Configuration Options
15  */
16 #define CONFIG_OMAP		/* in a TI OMAP core */
17 #define CONFIG_OMAP_GPIO
18 #define CONFIG_OMAP_COMMON
19 /* Common ARM Erratas */
20 #define CONFIG_ARM_ERRATA_454179
21 #define CONFIG_ARM_ERRATA_430973
22 #define CONFIG_ARM_ERRATA_621766
23 
24 #define CONFIG_SYS_TEXT_BASE 0x80008000
25 
26 #define CONFIG_SYS_CACHELINE_SIZE	64
27 
28 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
29 
30 #include <asm/arch/cpu.h>		/* get chip and board defs */
31 #include <asm/arch/omap.h>
32 
33 /*
34  * Display CPU and Board information
35  */
36 #define CONFIG_DISPLAY_CPUINFO
37 #define CONFIG_DISPLAY_BOARDINFO
38 
39 /* Clock Defines */
40 #define V_OSCK			26000000	/* Clock output from T2 */
41 #define V_SCLK			(V_OSCK >> 1)
42 
43 #define CONFIG_MISC_INIT_R
44 
45 #define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
46 #define CONFIG_SETUP_MEMORY_TAGS
47 #define CONFIG_INITRD_TAG
48 #define CONFIG_REVISION_TAG
49 
50 /*
51  * Size of malloc() pool
52  */
53 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
54 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
55 					2 * 1024 * 1024)
56 /*
57  * DDR related
58  */
59 #define CONFIG_OMAP3_MICRON_DDR		/* Micron DDR */
60 #define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
61 
62 /*
63  * Hardware drivers
64  */
65 
66 /*
67  * NS16550 Configuration
68  */
69 #define CONFIG_SYS_NS16550_SERIAL
70 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
71 #define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */
72 
73 /*
74  * select serial console configuration
75  */
76 #define CONFIG_CONS_INDEX		1
77 #define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
78 #define CONFIG_SERIAL1			/* UART1 */
79 
80 /* allow to overwrite serial and ethaddr */
81 #define CONFIG_ENV_OVERWRITE
82 #define CONFIG_BAUDRATE			115200
83 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
84 					115200}
85 #define CONFIG_MMC
86 #define CONFIG_OMAP_HSMMC
87 #define CONFIG_GENERIC_MMC
88 #define CONFIG_DOS_PARTITION
89 
90 /* EHCI */
91 #define CONFIG_OMAP3_GPIO_5
92 #define CONFIG_USB_EHCI
93 #define CONFIG_USB_EHCI_OMAP
94 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	25
95 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
96 #define CONFIG_USB_STORAGE
97 
98 /* commands to include */
99 #define CONFIG_CMD_NAND		/* NAND support			*/
100 #define CONFIG_CMD_EEPROM
101 
102 #define CONFIG_SYS_NO_FLASH
103 #define CONFIG_SYS_I2C
104 #define CONFIG_SYS_OMAP24_I2C_SPEED	400000
105 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
106 #define CONFIG_SYS_I2C_OMAP34XX
107 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
108 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
109 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
110 
111 /*
112  * Board NAND Info.
113  */
114 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
115 							/* to access */
116 							/* nand at CS0 */
117 
118 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
119 							/* NAND devices */
120 
121 #define CONFIG_AUTO_COMPLETE
122 
123 /*
124  * Miscellaneous configurable options
125  */
126 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
127 #define CONFIG_CMDLINE_EDITING
128 #define CONFIG_AUTO_COMPLETE
129 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
130 
131 /* Print Buffer Size */
132 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
133 					sizeof(CONFIG_SYS_PROMPT) + 16)
134 #define CONFIG_SYS_MAXARGS		32	/* max number of command */
135 						/* args */
136 /* Boot Argument Buffer Size */
137 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
138 /* memtest works on */
139 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
140 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
141 					0x01F00000) /* 31MB */
142 
143 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
144 								/* address */
145 
146 /*
147  * AM3517 has 12 GP timers, they can be driven by the system clock
148  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
149  * This rate is divided by a local divisor.
150  */
151 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
152 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
153 
154 /*
155  * Physical Memory Map
156  */
157 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
158 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
159 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
160 
161 /*
162  * FLASH and environment organization
163  */
164 
165 /* **** PISMO SUPPORT *** */
166 #define CONFIG_NAND
167 #define CONFIG_NAND_OMAP_GPMC
168 #define CONFIG_ENV_IS_IN_NAND
169 #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
170 
171 /* Redundant Environment */
172 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
173 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
174 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
175 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
176 						2 * CONFIG_SYS_ENV_SECT_SIZE)
177 #define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
178 
179 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
180 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
181 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
182 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
183 					 CONFIG_SYS_INIT_RAM_SIZE - \
184 					 GENERATED_GBL_DATA_SIZE)
185 
186 /*
187  * ethernet support, EMAC
188  *
189  */
190 #define CONFIG_DRIVER_TI_EMAC
191 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
192 #define CONFIG_MII
193 #define CONFIG_EMAC_MDIO_PHY_NUM	0
194 #define CONFIG_BOOTP_DNS
195 #define CONFIG_BOOTP_DNS2
196 #define CONFIG_BOOTP_SEND_HOSTNAME
197 #define CONFIG_NET_RETRY_COUNT 10
198 
199 /* Defines for SPL */
200 #define CONFIG_SPL_FRAMEWORK
201 #define CONFIG_SPL_BOARD_INIT
202 #define CONFIG_SPL_CONSOLE
203 #define CONFIG_SPL_NAND_SIMPLE
204 #define CONFIG_SPL_NAND_SOFTECC
205 #define CONFIG_SPL_NAND_WORKSPACE	0x8f07f000 /* below BSS */
206 
207 #define CONFIG_SPL_LIBCOMMON_SUPPORT
208 #define CONFIG_SPL_LIBDISK_SUPPORT
209 #define CONFIG_SPL_I2C_SUPPORT
210 #define CONFIG_SPL_MMC_SUPPORT
211 #define CONFIG_SPL_FAT_SUPPORT
212 #define CONFIG_SPL_LIBGENERIC_SUPPORT
213 #define CONFIG_SPL_SERIAL_SUPPORT
214 #define CONFIG_SPL_GPIO_SUPPORT
215 #define CONFIG_SPL_POWER_SUPPORT
216 #define CONFIG_SPL_NAND_SUPPORT
217 #define CONFIG_SPL_NAND_BASE
218 #define CONFIG_SPL_NAND_DRIVERS
219 #define CONFIG_SPL_NAND_ECC
220 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
221 
222 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
223 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
224 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
225 
226 #define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
227 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
228 #define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
229 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
230 
231 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
232 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
233 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
234 
235 /* FAT */
236 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
237 #define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"
238 
239 /* RAW SD card / eMMC */
240 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
241 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
242 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
243 
244 /* NAND boot config */
245 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
246 #define CONFIG_SYS_NAND_PAGE_COUNT	64
247 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
248 #define CONFIG_SYS_NAND_OOBSIZE		64
249 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
250 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
251 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
252 #define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
253 					 48, 49, 50, 51, 52, 53, 54, 55,\
254 					 56, 57, 58, 59, 60, 61, 62, 63}
255 #define CONFIG_SYS_NAND_ECCSIZE		256
256 #define CONFIG_SYS_NAND_ECCBYTES	3
257 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
258 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
259 
260 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
261 
262 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
263 #define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
264 
265 #define CONFIG_CMD_UBI
266 #define CONFIG_CMD_UBIFS
267 #define CONFIG_RBTREE
268 #define CONFIG_LZO
269 #define CONFIG_MTD_PARTITIONS
270 #define CONFIG_MTD_DEVICE
271 #define CONFIG_CMD_MTDPARTS
272 
273 /* Setup MTD for NAND on the SOM */
274 #define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
275 #define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO)," \
276 				"1m(u-boot),256k(env1)," \
277 				"256k(env2),6m(kernel),-(rootfs)"
278 
279 #define	CONFIG_TAM3517_SETTINGS						\
280 	"netdev=eth0\0"							\
281 	"nandargs=setenv bootargs root=${nandroot} "			\
282 		"rootfstype=${nandrootfstype}\0"			\
283 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
284 		"nfsroot=${serverip}:${rootpath}\0"			\
285 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
286 	"addip_sta=setenv bootargs ${bootargs} "			\
287 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
288 		":${hostname}:${netdev}:off panic=1\0"			\
289 	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
290 	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
291 		"else run addip_sta;fi\0"				\
292 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
293 	"addtty=setenv bootargs ${bootargs}"				\
294 		" console=ttyO0,${baudrate}\0"				\
295 	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
296 	"loadaddr=82000000\0"						\
297 	"kernel_addr_r=82000000\0"					\
298 	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
299 	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
300 	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
301 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
302 	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
303 		"bootm ${kernel_addr}\0"				\
304 	"nandboot=run nandargs addip addtty addmtd addmisc;"		\
305 		"nand read ${kernel_addr_r} kernel\0"			\
306 		"bootm ${kernel_addr_r}\0"				\
307 	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
308 		"run nfsargs addip addtty addmtd addmisc;"		\
309 		"bootm ${kernel_addr_r}\0"				\
310 	"net_self=if run net_self_load;then "				\
311 		"run ramargs addip addtty addmtd addmisc;"		\
312 		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
313 		"else echo Images not loades;fi\0"			\
314 	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
315 	"load=tftp ${loadaddr} ${u-boot}\0"				\
316 	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
317 	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
318 	"uboot_addr=0x80000\0"						\
319 	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
320 		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
321 	"updatemlo=nandecc hw;nand erase 0 20000;"			\
322 		"nand write ${loadaddr} 0 20000\0"			\
323 	"upd=if run load;then echo Updating u-boot;if run update;"	\
324 		"then echo U-Boot updated;"				\
325 			"else echo Error updating u-boot !;"		\
326 			"echo Board without bootloader !!;"		\
327 		"fi;"							\
328 		"else echo U-Boot not downloaded..exiting;fi\0"		\
329 
330 /*
331  * this is common code for all TAM3517 boards.
332  * MAC address is stored from manufacturer in
333  * I2C EEPROM
334  */
335 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
336 /*
337  * The I2C EEPROM on the TAM3517 contains
338  * mac address and production data
339  */
340 struct tam3517_module_info {
341 	char customer[48];
342 	char product[48];
343 
344 	/*
345 	 * bit 0~47  : sequence number
346 	 * bit 48~55 : week of year, from 0.
347 	 * bit 56~63 : year
348 	 */
349 	unsigned long long sequence_number;
350 
351 	/*
352 	 * bit 0~7   : revision fixed
353 	 * bit 8~15  : revision major
354 	 * bit 16~31 : TNxxx
355 	 */
356 	unsigned int revision;
357 	unsigned char eth_addr[4][8];
358 	unsigned char _rev[100];
359 };
360 
361 #define TAM3517_READ_EEPROM(info, ret) \
362 do {								\
363 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
364 	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,		\
365 		(void *)info, sizeof(*info)))			\
366 		ret = 1;					\
367 	else							\
368 		ret = 0;					\
369 } while (0)
370 
371 #define TAM3517_READ_MAC_FROM_EEPROM(info)			\
372 do {								\
373 	char buf[80], ethname[20];				\
374 	int i;							\
375 	memset(buf, 0, sizeof(buf));				\
376 	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) {	\
377 		sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X",	\
378 			(info)->eth_addr[i][5],			\
379 			(info)->eth_addr[i][4],			\
380 			(info)->eth_addr[i][3],			\
381 			(info)->eth_addr[i][2],			\
382 			(info)->eth_addr[i][1],			\
383 			(info)->eth_addr[i][0]);			\
384 								\
385 		if (i)						\
386 			sprintf(ethname, "eth%daddr", i);	\
387 		else						\
388 			strcpy(ethname, "ethaddr");		\
389 		printf("Setting %s from EEPROM with %s\n", ethname, buf);\
390 		setenv(ethname, buf);				\
391 	}							\
392 } while (0)
393 
394 /* The following macros are taken from Technexion's documentation */
395 #define TAM3517_sequence_number(info) \
396 	((info)->sequence_number % 0x1000000000000LL)
397 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
398 #define TAM3517_year(info) ((info)->sequence_number >> 56)
399 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
400 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
401 #define TAM3517_revision_tn(info) ((info)->revision >> 16)
402 
403 #define TAM3517_PRINT_SOM_INFO(info)				\
404 do {								\
405 	printf("Vendor:%s\n", (info)->customer);		\
406 	printf("SOM:   %s\n", (info)->product);			\
407 	printf("SeqNr: %02llu%02llu%012llu\n",			\
408 		TAM3517_year(info),				\
409 		TAM3517_week_of_year(info),			\
410 		TAM3517_sequence_number(info));			\
411 	printf("Rev:   TN%u %u.%u\n",				\
412 		TAM3517_revision_tn(info),			\
413 		TAM3517_revision_major(info),			\
414 		TAM3517_revision_fixed(info));			\
415 } while (0)
416 
417 #endif
418 
419 #endif /* __TAM3517_H */
420