1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifdef CONFIG_RAMBOOT_PBL 14 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 15 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 16 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg 17 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg 18 #endif 19 20 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 21 /* Set 1M boot space */ 22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 24 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_NO_FLASH 27 #endif 28 29 #define CONFIG_CMD_REGINFO 30 31 /* High Level Configuration Options */ 32 #define CONFIG_BOOKE 33 #define CONFIG_E500 /* BOOKE e500 family */ 34 #define CONFIG_E500MC /* BOOKE e500mc family */ 35 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 36 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 37 #define CONFIG_MP /* support multiple processors */ 38 39 #ifndef CONFIG_SYS_TEXT_BASE 40 #define CONFIG_SYS_TEXT_BASE 0xeff80000 41 #endif 42 43 #ifndef CONFIG_RESET_VECTOR_ADDRESS 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 45 #endif 46 47 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 48 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 49 #define CONFIG_FSL_IFC /* Enable IFC Support */ 50 #define CONFIG_PCI /* Enable PCI/PCIE */ 51 #define CONFIG_PCIE1 /* PCIE controler 1 */ 52 #define CONFIG_PCIE2 /* PCIE controler 2 */ 53 #define CONFIG_PCIE3 /* PCIE controler 3 */ 54 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 55 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 56 57 #define CONFIG_SYS_SRIO 58 #define CONFIG_SRIO1 /* SRIO port 1 */ 59 #define CONFIG_SRIO2 /* SRIO port 2 */ 60 #define CONFIG_SRIO_PCIE_BOOT_MASTER 61 62 #define CONFIG_FSL_LAW /* Use common FSL init code */ 63 64 #define CONFIG_ENV_OVERWRITE 65 66 #ifdef CONFIG_SYS_NO_FLASH 67 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 68 #define CONFIG_ENV_IS_NOWHERE 69 #endif 70 #else 71 #define CONFIG_FLASH_CFI_DRIVER 72 #define CONFIG_SYS_FLASH_CFI 73 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 74 #endif 75 76 #if defined(CONFIG_SPIFLASH) 77 #define CONFIG_SYS_EXTRA_ENV_RELOC 78 #define CONFIG_ENV_IS_IN_SPI_FLASH 79 #define CONFIG_ENV_SPI_BUS 0 80 #define CONFIG_ENV_SPI_CS 0 81 #define CONFIG_ENV_SPI_MAX_HZ 10000000 82 #define CONFIG_ENV_SPI_MODE 0 83 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 84 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 85 #define CONFIG_ENV_SECT_SIZE 0x10000 86 #elif defined(CONFIG_SDCARD) 87 #define CONFIG_SYS_EXTRA_ENV_RELOC 88 #define CONFIG_ENV_IS_IN_MMC 89 #define CONFIG_SYS_MMC_ENV_DEV 0 90 #define CONFIG_ENV_SIZE 0x2000 91 #define CONFIG_ENV_OFFSET (512 * 1097) 92 #elif defined(CONFIG_NAND) 93 #define CONFIG_SYS_EXTRA_ENV_RELOC 94 #define CONFIG_ENV_IS_IN_NAND 95 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 96 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 97 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 98 #define CONFIG_ENV_IS_IN_REMOTE 99 #define CONFIG_ENV_ADDR 0xffe20000 100 #define CONFIG_ENV_SIZE 0x2000 101 #elif defined(CONFIG_ENV_IS_NOWHERE) 102 #define CONFIG_ENV_SIZE 0x2000 103 #else 104 #define CONFIG_ENV_IS_IN_FLASH 105 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 106 #define CONFIG_ENV_SIZE 0x2000 107 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 108 #endif 109 110 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 111 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 112 113 #ifndef __ASSEMBLY__ 114 unsigned long get_board_sys_clk(void); 115 unsigned long get_board_ddr_clk(void); 116 #endif 117 118 /* 119 * These can be toggled for performance analysis, otherwise use default. 120 */ 121 #define CONFIG_SYS_CACHE_STASHING 122 #define CONFIG_BTB /* toggle branch predition */ 123 #define CONFIG_DDR_ECC 124 #ifdef CONFIG_DDR_ECC 125 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 126 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 127 #endif 128 129 #define CONFIG_ENABLE_36BIT_PHYS 130 131 #define CONFIG_ADDR_MAP 132 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 133 134 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 135 #define CONFIG_SYS_MEMTEST_END 0x00400000 136 #define CONFIG_SYS_ALT_MEMTEST 137 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 138 139 /* 140 * Config the L3 Cache as L3 SRAM 141 */ 142 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 143 144 #define CONFIG_SYS_DCSRBAR 0xf0000000 145 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 146 147 /* EEPROM */ 148 #define CONFIG_ID_EEPROM 149 #define CONFIG_SYS_I2C_EEPROM_NXID 150 #define CONFIG_SYS_EEPROM_BUS_NUM 0 151 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 152 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 153 154 /* 155 * DDR Setup 156 */ 157 #define CONFIG_VERY_BIG_RAM 158 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 159 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 160 161 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 162 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 163 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 164 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 165 166 #define CONFIG_DDR_SPD 167 #define CONFIG_FSL_DDR3 168 169 #define CONFIG_SYS_SPD_BUS_NUM 0 170 #define SPD_EEPROM_ADDRESS1 0x51 171 #define SPD_EEPROM_ADDRESS2 0x52 172 #define SPD_EEPROM_ADDRESS3 0x53 173 #define SPD_EEPROM_ADDRESS4 0x54 174 #define SPD_EEPROM_ADDRESS5 0x55 175 #define SPD_EEPROM_ADDRESS6 0x56 176 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 177 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 178 179 /* 180 * IFC Definitions 181 */ 182 #define CONFIG_SYS_FLASH_BASE 0xe0000000 183 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 184 185 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 186 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 187 + 0x8000000) | \ 188 CSPR_PORT_SIZE_16 | \ 189 CSPR_MSEL_NOR | \ 190 CSPR_V) 191 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 192 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 193 CSPR_PORT_SIZE_16 | \ 194 CSPR_MSEL_NOR | \ 195 CSPR_V) 196 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 197 /* NOR Flash Timing Params */ 198 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 199 200 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 201 FTIM0_NOR_TEADC(0x5) | \ 202 FTIM0_NOR_TEAHC(0x5)) 203 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 204 FTIM1_NOR_TRAD_NOR(0x1A) |\ 205 FTIM1_NOR_TSEQRAD_NOR(0x13)) 206 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 207 FTIM2_NOR_TCH(0x4) | \ 208 FTIM2_NOR_TWPH(0x0E) | \ 209 FTIM2_NOR_TWP(0x1c)) 210 #define CONFIG_SYS_NOR_FTIM3 0x0 211 212 #define CONFIG_SYS_FLASH_QUIET_TEST 213 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 214 215 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 216 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 217 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 218 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 219 220 #define CONFIG_SYS_FLASH_EMPTY_INFO 221 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 222 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 223 224 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 225 #define QIXIS_BASE 0xffdf0000 226 #define QIXIS_LBMAP_SWITCH 6 227 #define QIXIS_LBMAP_MASK 0x0f 228 #define QIXIS_LBMAP_SHIFT 0 229 #define QIXIS_LBMAP_DFLTBANK 0x00 230 #define QIXIS_LBMAP_ALTBANK 0x04 231 #define QIXIS_RST_CTL_RESET 0x83 232 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 233 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 234 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 235 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 236 237 #define CONFIG_SYS_CSPR3_EXT (0xf) 238 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 239 | CSPR_PORT_SIZE_8 \ 240 | CSPR_MSEL_GPCM \ 241 | CSPR_V) 242 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 243 #define CONFIG_SYS_CSOR3 0x0 244 /* QIXIS Timing parameters for IFC CS3 */ 245 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 246 FTIM0_GPCM_TEADC(0x0e) | \ 247 FTIM0_GPCM_TEAHC(0x0e)) 248 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 249 FTIM1_GPCM_TRAD(0x3f)) 250 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 251 FTIM2_GPCM_TCH(0x0) | \ 252 FTIM2_GPCM_TWP(0x1f)) 253 #define CONFIG_SYS_CS3_FTIM3 0x0 254 255 /* NAND Flash on IFC */ 256 #define CONFIG_NAND_FSL_IFC 257 #define CONFIG_SYS_NAND_BASE 0xff800000 258 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 259 260 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 261 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 262 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 263 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 264 | CSPR_V) 265 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 266 267 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 268 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 269 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 270 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 271 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 272 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 273 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 274 275 #define CONFIG_SYS_NAND_ONFI_DETECTION 276 277 /* ONFI NAND Flash mode0 Timing Params */ 278 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 279 FTIM0_NAND_TWP(0x18) | \ 280 FTIM0_NAND_TWCHT(0x07) | \ 281 FTIM0_NAND_TWH(0x0a)) 282 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 283 FTIM1_NAND_TWBE(0x39) | \ 284 FTIM1_NAND_TRR(0x0e) | \ 285 FTIM1_NAND_TRP(0x18)) 286 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 287 FTIM2_NAND_TREH(0x0a) | \ 288 FTIM2_NAND_TWHRE(0x1e)) 289 #define CONFIG_SYS_NAND_FTIM3 0x0 290 291 #define CONFIG_SYS_NAND_DDR_LAW 11 292 293 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 294 #define CONFIG_SYS_MAX_NAND_DEVICE 1 295 #define CONFIG_MTD_NAND_VERIFY_WRITE 296 #define CONFIG_CMD_NAND 297 298 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 299 300 #if defined(CONFIG_NAND) 301 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 302 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 303 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 304 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 305 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 306 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 307 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 308 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 309 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 310 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 311 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 312 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 313 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 314 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 315 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 316 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 317 #else 318 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 319 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 320 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 321 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 322 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 323 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 324 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 325 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 326 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 327 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 328 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 329 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 330 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 331 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 332 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 333 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 334 #endif 335 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 336 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 337 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 338 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 339 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 340 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 341 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 342 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 343 344 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 345 346 #if defined(CONFIG_RAMBOOT_PBL) 347 #define CONFIG_SYS_RAMBOOT 348 #endif 349 350 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 351 #define CONFIG_MISC_INIT_R 352 353 #define CONFIG_HWCONFIG 354 355 /* define to use L1 as initial stack */ 356 #define CONFIG_L1_INIT_RAM 357 #define CONFIG_SYS_INIT_RAM_LOCK 358 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 359 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 360 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 361 /* The assembler doesn't like typecast */ 362 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 363 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 364 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 365 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 366 367 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 368 GENERATED_GBL_DATA_SIZE) 369 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 370 371 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 372 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 373 374 /* Serial Port - controlled on board with jumper J8 375 * open - index 2 376 * shorted - index 1 377 */ 378 #define CONFIG_CONS_INDEX 1 379 #define CONFIG_SYS_NS16550 380 #define CONFIG_SYS_NS16550_SERIAL 381 #define CONFIG_SYS_NS16550_REG_SIZE 1 382 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 383 384 #define CONFIG_SYS_BAUDRATE_TABLE \ 385 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 386 387 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 388 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 389 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 390 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 391 392 /* Use the HUSH parser */ 393 #define CONFIG_SYS_HUSH_PARSER 394 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 395 396 /* pass open firmware flat tree */ 397 #define CONFIG_OF_LIBFDT 398 #define CONFIG_OF_BOARD_SETUP 399 #define CONFIG_OF_STDOUT_VIA_ALIAS 400 401 /* new uImage format support */ 402 #define CONFIG_FIT 403 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 404 405 /* I2C */ 406 #define CONFIG_SYS_I2C 407 #define CONFIG_SYS_I2C_FSL 408 #define CONFIG_SYS_FSL_I2C_SPEED 100000 409 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 410 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 411 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 412 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 413 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 414 415 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 416 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 417 418 #define I2C_MUX_CH_DEFAULT 0x8 419 #define I2C_MUX_CH_VOL_MONITOR 0xa 420 #define I2C_MUX_CH_VSC3316_FS 0xc 421 #define I2C_MUX_CH_VSC3316_BS 0xd 422 423 /* Voltage monitor on channel 2*/ 424 #define I2C_VOL_MONITOR_ADDR 0x40 425 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 426 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 427 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 428 429 /* VSC Crossbar switches */ 430 #define CONFIG_VSC_CROSSBAR 431 #define VSC3316_FSM_TX_ADDR 0x70 432 #define VSC3316_FSM_RX_ADDR 0x71 433 434 /* 435 * RapidIO 436 */ 437 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 438 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 439 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 440 441 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 442 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 443 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 444 445 /* 446 * for slave u-boot IMAGE instored in master memory space, 447 * PHYS must be aligned based on the SIZE 448 */ 449 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 450 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 451 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 452 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 453 /* 454 * for slave UCODE and ENV instored in master memory space, 455 * PHYS must be aligned based on the SIZE 456 */ 457 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 458 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 459 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 460 461 /* slave core release by master*/ 462 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 463 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 464 465 /* 466 * SRIO_PCIE_BOOT - SLAVE 467 */ 468 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 469 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 470 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 471 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 472 #endif 473 /* 474 * eSPI - Enhanced SPI 475 */ 476 #define CONFIG_FSL_ESPI 477 #define CONFIG_SPI_FLASH 478 #define CONFIG_SPI_FLASH_SST 479 #define CONFIG_CMD_SF 480 #define CONFIG_SF_DEFAULT_SPEED 10000000 481 #define CONFIG_SF_DEFAULT_MODE 0 482 483 /* 484 * General PCI 485 * Memory space is mapped 1-1, but I/O space must start from 0. 486 */ 487 488 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 489 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 490 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 491 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 492 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 493 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 494 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 495 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 496 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 497 498 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 499 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 500 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 501 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 502 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 503 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 504 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 505 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 506 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 507 508 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 509 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 510 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 511 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 512 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 513 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 514 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 515 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 516 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 517 518 /* controller 4, Base address 203000 */ 519 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 520 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 521 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 522 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 523 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 524 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 525 526 /* Qman/Bman */ 527 #ifndef CONFIG_NOBQFMAN 528 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 529 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 530 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 531 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 532 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 533 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 534 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 535 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 536 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 537 538 #define CONFIG_SYS_DPAA_FMAN 539 #define CONFIG_SYS_DPAA_PME 540 #define CONFIG_SYS_PMAN 541 #define CONFIG_SYS_DPAA_DCE 542 #define CONFIG_SYS_INTERLAKEN 543 544 /* Default address of microcode for the Linux Fman driver */ 545 #if defined(CONFIG_SPIFLASH) 546 /* 547 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 548 * env, so we got 0x110000. 549 */ 550 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 551 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 552 #elif defined(CONFIG_SDCARD) 553 /* 554 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 555 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 556 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 557 */ 558 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 559 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 560 #elif defined(CONFIG_NAND) 561 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 562 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 563 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 564 /* 565 * Slave has no ucode locally, it can fetch this from remote. When implementing 566 * in two corenet boards, slave's ucode could be stored in master's memory 567 * space, the address can be mapped from slave TLB->slave LAW-> 568 * slave SRIO or PCIE outbound window->master inbound window-> 569 * master LAW->the ucode address in master's memory space. 570 */ 571 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 572 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 573 #else 574 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 575 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 576 #endif 577 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 578 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 579 #endif /* CONFIG_NOBQFMAN */ 580 581 #ifdef CONFIG_SYS_DPAA_FMAN 582 #define CONFIG_FMAN_ENET 583 #define CONFIG_PHYLIB_10G 584 #define CONFIG_PHY_VITESSE 585 #define CONFIG_PHY_TERANETICS 586 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 587 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 588 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 589 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 590 #define FM1_10GEC1_PHY_ADDR 0x0 591 #define FM1_10GEC2_PHY_ADDR 0x1 592 #define FM2_10GEC1_PHY_ADDR 0x2 593 #define FM2_10GEC2_PHY_ADDR 0x3 594 #endif 595 596 #ifdef CONFIG_PCI 597 #define CONFIG_PCI_INDIRECT_BRIDGE 598 #define CONFIG_NET_MULTI 599 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 600 #define CONFIG_E1000 601 602 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 603 #define CONFIG_DOS_PARTITION 604 #endif /* CONFIG_PCI */ 605 606 /* SATA */ 607 #ifdef CONFIG_FSL_SATA_V2 608 #define CONFIG_LIBATA 609 #define CONFIG_FSL_SATA 610 611 #define CONFIG_SYS_SATA_MAX_DEVICE 2 612 #define CONFIG_SATA1 613 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 614 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 615 #define CONFIG_SATA2 616 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 617 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 618 619 #define CONFIG_LBA48 620 #define CONFIG_CMD_SATA 621 #define CONFIG_DOS_PARTITION 622 #define CONFIG_CMD_EXT2 623 #endif 624 625 #ifdef CONFIG_FMAN_ENET 626 #define CONFIG_MII /* MII PHY management */ 627 #define CONFIG_ETHPRIME "FM1@DTSEC1" 628 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 629 #endif 630 631 /* 632 * Environment 633 */ 634 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 635 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 636 637 /* 638 * Command line configuration. 639 */ 640 #include <config_cmd_default.h> 641 642 #define CONFIG_CMD_DHCP 643 #define CONFIG_CMD_ELF 644 #define CONFIG_CMD_ERRATA 645 #define CONFIG_CMD_GREPENV 646 #define CONFIG_CMD_IRQ 647 #define CONFIG_CMD_I2C 648 #define CONFIG_CMD_MII 649 #define CONFIG_CMD_PING 650 #define CONFIG_CMD_SETEXPR 651 652 #ifdef CONFIG_PCI 653 #define CONFIG_CMD_PCI 654 #define CONFIG_CMD_NET 655 #endif 656 657 /* 658 * USB 659 */ 660 #define CONFIG_CMD_USB 661 #define CONFIG_USB_STORAGE 662 #define CONFIG_USB_EHCI 663 #define CONFIG_USB_EHCI_FSL 664 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 665 #define CONFIG_CMD_EXT2 666 #define CONFIG_HAS_FSL_DR_USB 667 668 #define CONFIG_MMC 669 670 #ifdef CONFIG_MMC 671 #define CONFIG_FSL_ESDHC 672 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 673 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 674 #define CONFIG_CMD_MMC 675 #define CONFIG_GENERIC_MMC 676 #define CONFIG_CMD_EXT2 677 #define CONFIG_CMD_FAT 678 #define CONFIG_DOS_PARTITION 679 #endif 680 681 /* 682 * Miscellaneous configurable options 683 */ 684 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 685 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 686 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 687 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 688 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 689 #ifdef CONFIG_CMD_KGDB 690 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 691 #else 692 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 693 #endif 694 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 695 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 696 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 697 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ 698 699 /* 700 * For booting Linux, the board info and command line data 701 * have to be in the first 64 MB of memory, since this is 702 * the maximum mapped by the Linux kernel during initialization. 703 */ 704 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 705 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 706 707 #ifdef CONFIG_CMD_KGDB 708 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 709 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 710 #endif 711 712 /* 713 * Environment Configuration 714 */ 715 #define CONFIG_ROOTPATH "/opt/nfsroot" 716 #define CONFIG_BOOTFILE "uImage" 717 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 718 719 /* default location for tftp and bootm */ 720 #define CONFIG_LOADADDR 1000000 721 722 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 723 724 #define CONFIG_BAUDRATE 115200 725 726 #define __USB_PHY_TYPE utmi 727 728 /* 729 * T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be 730 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 731 * cacheline interleaving. It can be cacheline, page, bank, superbank. 732 * See doc/README.fsl-ddr for details. 733 */ 734 #ifdef CONFIG_PPC_T4240 735 #define CTRL_INTLV_PREFERED 3way_4KB 736 #else 737 #define CTRL_INTLV_PREFERED cacheline 738 #endif 739 740 #define CONFIG_EXTRA_ENV_SETTINGS \ 741 "hwconfig=fsl_ddr:" \ 742 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 743 "bank_intlv=auto;" \ 744 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 745 "netdev=eth0\0" \ 746 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 747 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 748 "tftpflash=tftpboot $loadaddr $uboot && " \ 749 "protect off $ubootaddr +$filesize && " \ 750 "erase $ubootaddr +$filesize && " \ 751 "cp.b $loadaddr $ubootaddr $filesize && " \ 752 "protect on $ubootaddr +$filesize && " \ 753 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 754 "consoledev=ttyS0\0" \ 755 "ramdiskaddr=2000000\0" \ 756 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 757 "fdtaddr=c00000\0" \ 758 "fdtfile=t4240qds/t4240qds.dtb\0" \ 759 "bdev=sda3\0" \ 760 "c=ffe\0" 761 762 /* For emulation this causes u-boot to jump to the start of the proof point 763 app code automatically */ 764 #define CONFIG_PROOF_POINTS \ 765 "setenv bootargs root=/dev/$bdev rw " \ 766 "console=$consoledev,$baudrate $othbootargs;" \ 767 "cpu 1 release 0x29000000 - - -;" \ 768 "cpu 2 release 0x29000000 - - -;" \ 769 "cpu 3 release 0x29000000 - - -;" \ 770 "cpu 4 release 0x29000000 - - -;" \ 771 "cpu 5 release 0x29000000 - - -;" \ 772 "cpu 6 release 0x29000000 - - -;" \ 773 "cpu 7 release 0x29000000 - - -;" \ 774 "go 0x29000000" 775 776 #define CONFIG_HVBOOT \ 777 "setenv bootargs config-addr=0x60000000; " \ 778 "bootm 0x01000000 - 0x00f00000" 779 780 #define CONFIG_ALU \ 781 "setenv bootargs root=/dev/$bdev rw " \ 782 "console=$consoledev,$baudrate $othbootargs;" \ 783 "cpu 1 release 0x01000000 - - -;" \ 784 "cpu 2 release 0x01000000 - - -;" \ 785 "cpu 3 release 0x01000000 - - -;" \ 786 "cpu 4 release 0x01000000 - - -;" \ 787 "cpu 5 release 0x01000000 - - -;" \ 788 "cpu 6 release 0x01000000 - - -;" \ 789 "cpu 7 release 0x01000000 - - -;" \ 790 "go 0x01000000" 791 792 #define CONFIG_LINUX \ 793 "setenv bootargs root=/dev/ram rw " \ 794 "console=$consoledev,$baudrate $othbootargs;" \ 795 "setenv ramdiskaddr 0x02000000;" \ 796 "setenv fdtaddr 0x00c00000;" \ 797 "setenv loadaddr 0x1000000;" \ 798 "bootm $loadaddr $ramdiskaddr $fdtaddr" 799 800 #define CONFIG_HDBOOT \ 801 "setenv bootargs root=/dev/$bdev rw " \ 802 "console=$consoledev,$baudrate $othbootargs;" \ 803 "tftp $loadaddr $bootfile;" \ 804 "tftp $fdtaddr $fdtfile;" \ 805 "bootm $loadaddr - $fdtaddr" 806 807 #define CONFIG_NFSBOOTCOMMAND \ 808 "setenv bootargs root=/dev/nfs rw " \ 809 "nfsroot=$serverip:$rootpath " \ 810 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 811 "console=$consoledev,$baudrate $othbootargs;" \ 812 "tftp $loadaddr $bootfile;" \ 813 "tftp $fdtaddr $fdtfile;" \ 814 "bootm $loadaddr - $fdtaddr" 815 816 #define CONFIG_RAMBOOTCOMMAND \ 817 "setenv bootargs root=/dev/ram rw " \ 818 "console=$consoledev,$baudrate $othbootargs;" \ 819 "tftp $ramdiskaddr $ramdiskfile;" \ 820 "tftp $loadaddr $bootfile;" \ 821 "tftp $fdtaddr $fdtfile;" \ 822 "bootm $loadaddr $ramdiskaddr $fdtaddr" 823 824 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 825 826 #ifdef CONFIG_SECURE_BOOT 827 #include <asm/fsl_secure_boot.h> 828 #endif 829 830 #endif /* __CONFIG_H */ 831