1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __T4QDS_H 11 #define __T4QDS_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 15 #define CONFIG_MP /* support multiple processors */ 16 17 #ifndef CONFIG_RESET_VECTOR_ADDRESS 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 19 #endif 20 21 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 22 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 23 #define CONFIG_PCIE1 /* PCIE controller 1 */ 24 #define CONFIG_PCIE2 /* PCIE controller 2 */ 25 #define CONFIG_PCIE3 /* PCIE controller 3 */ 26 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 27 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 28 29 #define CONFIG_SYS_SRIO 30 #define CONFIG_SRIO1 /* SRIO port 1 */ 31 #define CONFIG_SRIO2 /* SRIO port 2 */ 32 33 #define CONFIG_ENV_OVERWRITE 34 35 /* 36 * These can be toggled for performance analysis, otherwise use default. 37 */ 38 #define CONFIG_SYS_CACHE_STASHING 39 #define CONFIG_BTB /* toggle branch predition */ 40 #ifdef CONFIG_DDR_ECC 41 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 42 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 43 #endif 44 45 #define CONFIG_ENABLE_36BIT_PHYS 46 47 #define CONFIG_ADDR_MAP 48 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 49 50 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 51 #define CONFIG_SYS_MEMTEST_END 0x00400000 52 53 /* 54 * Config the L3 Cache as L3 SRAM 55 */ 56 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 57 #define CONFIG_SYS_L3_SIZE (512 << 10) 58 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 59 #ifdef CONFIG_RAMBOOT_PBL 60 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 61 #endif 62 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 63 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 64 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 65 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 66 67 #define CONFIG_SYS_DCSRBAR 0xf0000000 68 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 69 70 /* 71 * DDR Setup 72 */ 73 #define CONFIG_VERY_BIG_RAM 74 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 75 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 76 77 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 78 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 79 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 80 81 #define CONFIG_DDR_SPD 82 83 /* 84 * IFC Definitions 85 */ 86 #define CONFIG_SYS_FLASH_BASE 0xe0000000 87 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 88 89 #ifdef CONFIG_SPL_BUILD 90 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 91 #else 92 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 93 #endif 94 95 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 96 #define CONFIG_MISC_INIT_R 97 98 #define CONFIG_HWCONFIG 99 100 /* define to use L1 as initial stack */ 101 #define CONFIG_L1_INIT_RAM 102 #define CONFIG_SYS_INIT_RAM_LOCK 103 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 104 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 105 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 106 /* The assembler doesn't like typecast */ 107 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 108 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 109 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 110 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 111 112 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 113 GENERATED_GBL_DATA_SIZE) 114 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 115 116 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 117 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 118 119 /* Serial Port - controlled on board with jumper J8 120 * open - index 2 121 * shorted - index 1 122 */ 123 #define CONFIG_SYS_NS16550_SERIAL 124 #define CONFIG_SYS_NS16550_REG_SIZE 1 125 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 126 127 #define CONFIG_SYS_BAUDRATE_TABLE \ 128 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 129 130 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 131 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 132 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 133 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 134 135 /* I2C */ 136 #define CONFIG_SYS_I2C 137 #define CONFIG_SYS_I2C_FSL 138 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 139 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 140 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 141 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 142 143 /* 144 * RapidIO 145 */ 146 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 147 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 148 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 149 150 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 151 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 152 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 153 154 /* 155 * General PCI 156 * Memory space is mapped 1-1, but I/O space must start from 0. 157 */ 158 159 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 160 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 161 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 162 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 163 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 164 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 165 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 166 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 167 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 168 169 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 170 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 171 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 172 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 173 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 174 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 175 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 176 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 177 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 178 179 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 180 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 181 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 182 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 183 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 184 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 185 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 186 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 187 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 188 189 /* controller 4, Base address 203000 */ 190 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 191 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 192 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 193 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 194 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 195 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 196 197 #ifdef CONFIG_PCI 198 #define CONFIG_PCI_INDIRECT_BRIDGE 199 200 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 201 #endif /* CONFIG_PCI */ 202 203 /* SATA */ 204 #ifdef CONFIG_FSL_SATA_V2 205 #define CONFIG_SYS_SATA_MAX_DEVICE 2 206 #define CONFIG_SATA1 207 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 208 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 209 #define CONFIG_SATA2 210 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 211 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 212 213 #define CONFIG_LBA48 214 #endif 215 216 #ifdef CONFIG_FMAN_ENET 217 #define CONFIG_MII /* MII PHY management */ 218 #define CONFIG_ETHPRIME "FM1@DTSEC1" 219 #endif 220 221 /* 222 * Environment 223 */ 224 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 225 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 226 227 /* 228 * Command line configuration. 229 */ 230 231 /* 232 * Miscellaneous configurable options 233 */ 234 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 235 236 /* 237 * For booting Linux, the board info and command line data 238 * have to be in the first 64 MB of memory, since this is 239 * the maximum mapped by the Linux kernel during initialization. 240 */ 241 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 242 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 243 244 #ifdef CONFIG_CMD_KGDB 245 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 246 #endif 247 248 /* 249 * Environment Configuration 250 */ 251 #define CONFIG_ROOTPATH "/opt/nfsroot" 252 #define CONFIG_BOOTFILE "uImage" 253 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 254 255 /* default location for tftp and bootm */ 256 #define CONFIG_LOADADDR 1000000 257 258 #define CONFIG_HVBOOT \ 259 "setenv bootargs config-addr=0x60000000; " \ 260 "bootm 0x01000000 - 0x00f00000" 261 262 #endif /* __CONFIG_H */ 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