1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __T4QDS_H 11 #define __T4QDS_H 12 13 #define CONFIG_SYS_GENERIC_BOARD 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_CMD_REGINFO 16 17 /* High Level Configuration Options */ 18 #define CONFIG_BOOKE 19 #define CONFIG_E500 /* BOOKE e500 family */ 20 #define CONFIG_E500MC /* BOOKE e500mc family */ 21 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 22 #define CONFIG_MP /* support multiple processors */ 23 24 #ifndef CONFIG_SYS_TEXT_BASE 25 #define CONFIG_SYS_TEXT_BASE 0xeff40000 26 #endif 27 28 #ifndef CONFIG_RESET_VECTOR_ADDRESS 29 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 30 #endif 31 32 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 33 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 34 #define CONFIG_FSL_IFC /* Enable IFC Support */ 35 #define CONFIG_PCI /* Enable PCI/PCIE */ 36 #define CONFIG_PCIE1 /* PCIE controler 1 */ 37 #define CONFIG_PCIE2 /* PCIE controler 2 */ 38 #define CONFIG_PCIE3 /* PCIE controler 3 */ 39 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 40 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 41 42 #define CONFIG_SYS_SRIO 43 #define CONFIG_SRIO1 /* SRIO port 1 */ 44 #define CONFIG_SRIO2 /* SRIO port 2 */ 45 46 #define CONFIG_FSL_LAW /* Use common FSL init code */ 47 48 #define CONFIG_ENV_OVERWRITE 49 50 /* 51 * These can be toggled for performance analysis, otherwise use default. 52 */ 53 #define CONFIG_SYS_CACHE_STASHING 54 #define CONFIG_BTB /* toggle branch predition */ 55 #ifdef CONFIG_DDR_ECC 56 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 57 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 58 #endif 59 60 #define CONFIG_ENABLE_36BIT_PHYS 61 62 #define CONFIG_ADDR_MAP 63 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 64 65 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 66 #define CONFIG_SYS_MEMTEST_END 0x00400000 67 #define CONFIG_SYS_ALT_MEMTEST 68 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 69 70 /* 71 * Config the L3 Cache as L3 SRAM 72 */ 73 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 74 #define CONFIG_SYS_L3_SIZE (512 << 10) 75 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 76 #ifdef CONFIG_RAMBOOT_PBL 77 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 78 #endif 79 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 80 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 81 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 82 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 83 84 #define CONFIG_SYS_DCSRBAR 0xf0000000 85 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 86 87 /* 88 * DDR Setup 89 */ 90 #define CONFIG_VERY_BIG_RAM 91 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 92 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 93 94 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 95 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 96 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 97 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 98 99 #define CONFIG_DDR_SPD 100 #define CONFIG_SYS_FSL_DDR3 101 102 103 /* 104 * IFC Definitions 105 */ 106 #define CONFIG_SYS_FLASH_BASE 0xe0000000 107 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 108 109 110 #ifdef CONFIG_SPL_BUILD 111 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 112 #else 113 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 114 #endif 115 116 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 117 #define CONFIG_MISC_INIT_R 118 119 #define CONFIG_HWCONFIG 120 121 /* define to use L1 as initial stack */ 122 #define CONFIG_L1_INIT_RAM 123 #define CONFIG_SYS_INIT_RAM_LOCK 124 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 125 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 126 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 127 /* The assembler doesn't like typecast */ 128 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 129 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 130 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 131 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 132 133 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 134 GENERATED_GBL_DATA_SIZE) 135 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 136 137 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 138 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 139 140 /* Serial Port - controlled on board with jumper J8 141 * open - index 2 142 * shorted - index 1 143 */ 144 #define CONFIG_CONS_INDEX 1 145 #define CONFIG_SYS_NS16550 146 #define CONFIG_SYS_NS16550_SERIAL 147 #define CONFIG_SYS_NS16550_REG_SIZE 1 148 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 149 150 #define CONFIG_SYS_BAUDRATE_TABLE \ 151 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 152 153 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 154 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 155 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 156 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 157 158 /* Use the HUSH parser */ 159 #define CONFIG_SYS_HUSH_PARSER 160 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 161 162 /* pass open firmware flat tree */ 163 #define CONFIG_OF_LIBFDT 164 #define CONFIG_OF_BOARD_SETUP 165 #define CONFIG_OF_STDOUT_VIA_ALIAS 166 167 /* new uImage format support */ 168 #define CONFIG_FIT 169 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 170 171 /* I2C */ 172 #define CONFIG_SYS_I2C 173 #define CONFIG_SYS_I2C_FSL 174 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 175 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 176 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 177 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 178 179 /* 180 * RapidIO 181 */ 182 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 183 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 184 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 185 186 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 187 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 188 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 189 190 /* 191 * General PCI 192 * Memory space is mapped 1-1, but I/O space must start from 0. 193 */ 194 195 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 196 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 197 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 198 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 199 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 200 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 201 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 202 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 203 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 204 205 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 206 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 207 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 208 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 209 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 210 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 211 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 212 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 213 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 214 215 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 216 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 217 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 218 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 219 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 220 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 221 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 222 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 223 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 224 225 /* controller 4, Base address 203000 */ 226 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 227 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 228 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 229 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 230 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 231 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 232 233 #ifdef CONFIG_PCI 234 #define CONFIG_PCI_INDIRECT_BRIDGE 235 #define CONFIG_NET_MULTI 236 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 237 #define CONFIG_E1000 238 239 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 240 #define CONFIG_DOS_PARTITION 241 #endif /* CONFIG_PCI */ 242 243 /* SATA */ 244 #ifdef CONFIG_FSL_SATA_V2 245 #define CONFIG_LIBATA 246 #define CONFIG_FSL_SATA 247 248 #define CONFIG_SYS_SATA_MAX_DEVICE 2 249 #define CONFIG_SATA1 250 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 251 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 252 #define CONFIG_SATA2 253 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 254 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 255 256 #define CONFIG_LBA48 257 #define CONFIG_CMD_SATA 258 #define CONFIG_DOS_PARTITION 259 #define CONFIG_CMD_EXT2 260 #endif 261 262 #ifdef CONFIG_FMAN_ENET 263 #define CONFIG_MII /* MII PHY management */ 264 #define CONFIG_ETHPRIME "FM1@DTSEC1" 265 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 266 #endif 267 268 /* 269 * Environment 270 */ 271 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 272 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 273 274 /* 275 * Command line configuration. 276 */ 277 #include <config_cmd_default.h> 278 279 #define CONFIG_CMD_DHCP 280 #define CONFIG_CMD_ELF 281 #define CONFIG_CMD_ERRATA 282 #define CONFIG_CMD_GREPENV 283 #define CONFIG_CMD_IRQ 284 #define CONFIG_CMD_I2C 285 #define CONFIG_CMD_MII 286 #define CONFIG_CMD_PING 287 #define CONFIG_CMD_SETEXPR 288 289 #ifdef CONFIG_PCI 290 #define CONFIG_CMD_PCI 291 #define CONFIG_CMD_NET 292 #endif 293 294 /* 295 * Miscellaneous configurable options 296 */ 297 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 298 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 299 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 300 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 301 #ifdef CONFIG_CMD_KGDB 302 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 303 #else 304 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 305 #endif 306 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 307 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 308 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 309 310 /* 311 * For booting Linux, the board info and command line data 312 * have to be in the first 64 MB of memory, since this is 313 * the maximum mapped by the Linux kernel during initialization. 314 */ 315 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 316 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 317 318 #ifdef CONFIG_CMD_KGDB 319 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 320 #endif 321 322 /* 323 * Environment Configuration 324 */ 325 #define CONFIG_ROOTPATH "/opt/nfsroot" 326 #define CONFIG_BOOTFILE "uImage" 327 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 328 329 /* default location for tftp and bootm */ 330 #define CONFIG_LOADADDR 1000000 331 332 333 #define CONFIG_BAUDRATE 115200 334 335 #define CONFIG_HVBOOT \ 336 "setenv bootargs config-addr=0x60000000; " \ 337 "bootm 0x01000000 - 0x00f00000" 338 339 #endif /* __CONFIG_H */ 340