1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * Corenet DS style board configuration file 8 */ 9 #ifndef __T4QDS_H 10 #define __T4QDS_H 11 12 /* High Level Configuration Options */ 13 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 14 15 #ifndef CONFIG_RESET_VECTOR_ADDRESS 16 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 17 #endif 18 19 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 20 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 21 #define CONFIG_PCIE1 /* PCIE controller 1 */ 22 #define CONFIG_PCIE2 /* PCIE controller 2 */ 23 #define CONFIG_PCIE3 /* PCIE controller 3 */ 24 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 25 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 26 27 #define CONFIG_SYS_SRIO 28 #define CONFIG_SRIO1 /* SRIO port 1 */ 29 #define CONFIG_SRIO2 /* SRIO port 2 */ 30 31 #define CONFIG_ENV_OVERWRITE 32 33 /* 34 * These can be toggled for performance analysis, otherwise use default. 35 */ 36 #define CONFIG_SYS_CACHE_STASHING 37 #define CONFIG_BTB /* toggle branch predition */ 38 #ifdef CONFIG_DDR_ECC 39 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 40 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 41 #endif 42 43 #define CONFIG_ENABLE_36BIT_PHYS 44 45 #define CONFIG_ADDR_MAP 46 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 47 48 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 49 #define CONFIG_SYS_MEMTEST_END 0x00400000 50 51 /* 52 * Config the L3 Cache as L3 SRAM 53 */ 54 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 55 #define CONFIG_SYS_L3_SIZE (512 << 10) 56 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 57 #ifdef CONFIG_RAMBOOT_PBL 58 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 59 #endif 60 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 61 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 62 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 63 64 #define CONFIG_SYS_DCSRBAR 0xf0000000 65 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 66 67 /* 68 * DDR Setup 69 */ 70 #define CONFIG_VERY_BIG_RAM 71 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 72 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 73 74 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 75 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 76 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 77 78 #define CONFIG_DDR_SPD 79 80 /* 81 * IFC Definitions 82 */ 83 #define CONFIG_SYS_FLASH_BASE 0xe0000000 84 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 85 86 #ifdef CONFIG_SPL_BUILD 87 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 88 #else 89 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 90 #endif 91 92 #define CONFIG_MISC_INIT_R 93 94 #define CONFIG_HWCONFIG 95 96 /* define to use L1 as initial stack */ 97 #define CONFIG_L1_INIT_RAM 98 #define CONFIG_SYS_INIT_RAM_LOCK 99 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 100 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 101 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 102 /* The assembler doesn't like typecast */ 103 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 104 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 105 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 106 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 107 108 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 109 GENERATED_GBL_DATA_SIZE) 110 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 111 112 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 113 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 114 115 /* Serial Port - controlled on board with jumper J8 116 * open - index 2 117 * shorted - index 1 118 */ 119 #define CONFIG_SYS_NS16550_SERIAL 120 #define CONFIG_SYS_NS16550_REG_SIZE 1 121 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 122 123 #define CONFIG_SYS_BAUDRATE_TABLE \ 124 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 125 126 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 127 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 128 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 129 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 130 131 /* I2C */ 132 #define CONFIG_SYS_I2C 133 #define CONFIG_SYS_I2C_FSL 134 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 135 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 136 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 137 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 138 139 /* 140 * RapidIO 141 */ 142 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 143 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 144 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 145 146 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 147 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 148 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 149 150 /* 151 * General PCI 152 * Memory space is mapped 1-1, but I/O space must start from 0. 153 */ 154 155 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 156 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 157 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 158 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 159 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 160 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 161 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 162 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 163 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 164 165 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 166 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 167 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 168 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 169 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 170 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 171 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 172 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 173 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 174 175 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 176 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 177 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 178 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 179 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 180 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 181 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 182 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 183 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 184 185 /* controller 4, Base address 203000 */ 186 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 187 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 188 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 189 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 190 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 191 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 192 193 #ifdef CONFIG_PCI 194 #define CONFIG_PCI_INDIRECT_BRIDGE 195 196 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 197 #endif /* CONFIG_PCI */ 198 199 /* SATA */ 200 #ifdef CONFIG_FSL_SATA_V2 201 #define CONFIG_SYS_SATA_MAX_DEVICE 2 202 #define CONFIG_SATA1 203 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 204 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 205 #define CONFIG_SATA2 206 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 207 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 208 209 #define CONFIG_LBA48 210 #endif 211 212 #ifdef CONFIG_FMAN_ENET 213 #define CONFIG_MII /* MII PHY management */ 214 #define CONFIG_ETHPRIME "FM1@DTSEC1" 215 #endif 216 217 /* 218 * Environment 219 */ 220 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 221 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 222 223 /* 224 * Command line configuration. 225 */ 226 227 /* 228 * Miscellaneous configurable options 229 */ 230 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 231 232 /* 233 * For booting Linux, the board info and command line data 234 * have to be in the first 64 MB of memory, since this is 235 * the maximum mapped by the Linux kernel during initialization. 236 */ 237 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 238 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 239 240 #ifdef CONFIG_CMD_KGDB 241 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 242 #endif 243 244 /* 245 * Environment Configuration 246 */ 247 #define CONFIG_ROOTPATH "/opt/nfsroot" 248 #define CONFIG_BOOTFILE "uImage" 249 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 250 251 /* default location for tftp and bootm */ 252 #define CONFIG_LOADADDR 1000000 253 254 #define CONFIG_HVBOOT \ 255 "setenv bootargs config-addr=0x60000000; " \ 256 "bootm 0x01000000 - 0x00f00000" 257 258 #endif /* __CONFIG_H */ 259