1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __T4QDS_H 11 #define __T4QDS_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 15 #define CONFIG_MP /* support multiple processors */ 16 17 #ifndef CONFIG_SYS_TEXT_BASE 18 #define CONFIG_SYS_TEXT_BASE 0xeff40000 19 #endif 20 21 #ifndef CONFIG_RESET_VECTOR_ADDRESS 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 23 #endif 24 25 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 26 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 27 #define CONFIG_PCIE1 /* PCIE controller 1 */ 28 #define CONFIG_PCIE2 /* PCIE controller 2 */ 29 #define CONFIG_PCIE3 /* PCIE controller 3 */ 30 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 31 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 32 33 #define CONFIG_SYS_SRIO 34 #define CONFIG_SRIO1 /* SRIO port 1 */ 35 #define CONFIG_SRIO2 /* SRIO port 2 */ 36 37 #define CONFIG_ENV_OVERWRITE 38 39 /* 40 * These can be toggled for performance analysis, otherwise use default. 41 */ 42 #define CONFIG_SYS_CACHE_STASHING 43 #define CONFIG_BTB /* toggle branch predition */ 44 #ifdef CONFIG_DDR_ECC 45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 47 #endif 48 49 #define CONFIG_ENABLE_36BIT_PHYS 50 51 #define CONFIG_ADDR_MAP 52 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 53 54 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 55 #define CONFIG_SYS_MEMTEST_END 0x00400000 56 #define CONFIG_SYS_ALT_MEMTEST 57 58 /* 59 * Config the L3 Cache as L3 SRAM 60 */ 61 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 62 #define CONFIG_SYS_L3_SIZE (512 << 10) 63 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 64 #ifdef CONFIG_RAMBOOT_PBL 65 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 66 #endif 67 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 68 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 69 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 70 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 71 72 #define CONFIG_SYS_DCSRBAR 0xf0000000 73 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 74 75 /* 76 * DDR Setup 77 */ 78 #define CONFIG_VERY_BIG_RAM 79 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 80 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 81 82 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 83 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 84 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 85 86 #define CONFIG_DDR_SPD 87 88 /* 89 * IFC Definitions 90 */ 91 #define CONFIG_SYS_FLASH_BASE 0xe0000000 92 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 93 94 #ifdef CONFIG_SPL_BUILD 95 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 96 #else 97 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 98 #endif 99 100 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 101 #define CONFIG_MISC_INIT_R 102 103 #define CONFIG_HWCONFIG 104 105 /* define to use L1 as initial stack */ 106 #define CONFIG_L1_INIT_RAM 107 #define CONFIG_SYS_INIT_RAM_LOCK 108 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 109 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 110 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 111 /* The assembler doesn't like typecast */ 112 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 113 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 114 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 115 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 116 117 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 118 GENERATED_GBL_DATA_SIZE) 119 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 120 121 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 122 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 123 124 /* Serial Port - controlled on board with jumper J8 125 * open - index 2 126 * shorted - index 1 127 */ 128 #define CONFIG_CONS_INDEX 1 129 #define CONFIG_SYS_NS16550_SERIAL 130 #define CONFIG_SYS_NS16550_REG_SIZE 1 131 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 132 133 #define CONFIG_SYS_BAUDRATE_TABLE \ 134 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 135 136 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 137 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 138 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 139 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 140 141 /* I2C */ 142 #define CONFIG_SYS_I2C 143 #define CONFIG_SYS_I2C_FSL 144 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 145 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 146 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 147 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 148 149 /* 150 * RapidIO 151 */ 152 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 153 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 154 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 155 156 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 157 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 158 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 159 160 /* 161 * General PCI 162 * Memory space is mapped 1-1, but I/O space must start from 0. 163 */ 164 165 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 166 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 167 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 168 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 169 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 170 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 171 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 172 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 173 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 174 175 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 176 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 177 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 178 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 179 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 180 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 181 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 182 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 183 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 184 185 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 186 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 187 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 188 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 189 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 190 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 191 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 192 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 193 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 194 195 /* controller 4, Base address 203000 */ 196 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 197 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 198 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 199 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 200 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 201 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 202 203 #ifdef CONFIG_PCI 204 #define CONFIG_PCI_INDIRECT_BRIDGE 205 206 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 207 #endif /* CONFIG_PCI */ 208 209 /* SATA */ 210 #ifdef CONFIG_FSL_SATA_V2 211 #define CONFIG_SYS_SATA_MAX_DEVICE 2 212 #define CONFIG_SATA1 213 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 214 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 215 #define CONFIG_SATA2 216 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 217 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 218 219 #define CONFIG_LBA48 220 #endif 221 222 #ifdef CONFIG_FMAN_ENET 223 #define CONFIG_MII /* MII PHY management */ 224 #define CONFIG_ETHPRIME "FM1@DTSEC1" 225 #endif 226 227 /* 228 * Environment 229 */ 230 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 231 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 232 233 /* 234 * Command line configuration. 235 */ 236 237 /* 238 * Miscellaneous configurable options 239 */ 240 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 241 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 242 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 243 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 244 245 /* 246 * For booting Linux, the board info and command line data 247 * have to be in the first 64 MB of memory, since this is 248 * the maximum mapped by the Linux kernel during initialization. 249 */ 250 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 251 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 252 253 #ifdef CONFIG_CMD_KGDB 254 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 255 #endif 256 257 /* 258 * Environment Configuration 259 */ 260 #define CONFIG_ROOTPATH "/opt/nfsroot" 261 #define CONFIG_BOOTFILE "uImage" 262 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 263 264 /* default location for tftp and bootm */ 265 #define CONFIG_LOADADDR 1000000 266 267 #define CONFIG_HVBOOT \ 268 "setenv bootargs config-addr=0x60000000; " \ 269 "bootm 0x01000000 - 0x00f00000" 270 271 #endif /* __CONFIG_H */ 272