1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * Corenet DS style board configuration file 8 */ 9 #ifndef __T4QDS_H 10 #define __T4QDS_H 11 12 /* High Level Configuration Options */ 13 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 14 15 #ifndef CONFIG_RESET_VECTOR_ADDRESS 16 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 17 #endif 18 19 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 20 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 21 #define CONFIG_PCIE1 /* PCIE controller 1 */ 22 #define CONFIG_PCIE2 /* PCIE controller 2 */ 23 #define CONFIG_PCIE3 /* PCIE controller 3 */ 24 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 25 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 26 27 #define CONFIG_SYS_SRIO 28 #define CONFIG_SRIO1 /* SRIO port 1 */ 29 #define CONFIG_SRIO2 /* SRIO port 2 */ 30 31 #define CONFIG_ENV_OVERWRITE 32 33 /* 34 * These can be toggled for performance analysis, otherwise use default. 35 */ 36 #define CONFIG_SYS_CACHE_STASHING 37 #define CONFIG_BTB /* toggle branch predition */ 38 #ifdef CONFIG_DDR_ECC 39 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 40 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 41 #endif 42 43 #define CONFIG_ENABLE_36BIT_PHYS 44 45 #define CONFIG_ADDR_MAP 46 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 47 48 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 49 #define CONFIG_SYS_MEMTEST_END 0x00400000 50 51 /* 52 * Config the L3 Cache as L3 SRAM 53 */ 54 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 55 #define CONFIG_SYS_L3_SIZE (512 << 10) 56 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 57 #ifdef CONFIG_RAMBOOT_PBL 58 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 59 #endif 60 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 61 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 62 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 63 64 #define CONFIG_SYS_DCSRBAR 0xf0000000 65 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 66 67 /* 68 * DDR Setup 69 */ 70 #define CONFIG_VERY_BIG_RAM 71 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 72 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 73 74 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 75 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 76 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 77 78 #define CONFIG_DDR_SPD 79 80 /* 81 * IFC Definitions 82 */ 83 #define CONFIG_SYS_FLASH_BASE 0xe0000000 84 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 85 86 #ifdef CONFIG_SPL_BUILD 87 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 88 #else 89 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 90 #endif 91 92 #define CONFIG_HWCONFIG 93 94 /* define to use L1 as initial stack */ 95 #define CONFIG_L1_INIT_RAM 96 #define CONFIG_SYS_INIT_RAM_LOCK 97 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 98 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 99 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 100 /* The assembler doesn't like typecast */ 101 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 102 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 103 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 104 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 105 106 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 107 GENERATED_GBL_DATA_SIZE) 108 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 109 110 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 111 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 112 113 /* Serial Port - controlled on board with jumper J8 114 * open - index 2 115 * shorted - index 1 116 */ 117 #define CONFIG_SYS_NS16550_SERIAL 118 #define CONFIG_SYS_NS16550_REG_SIZE 1 119 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 120 121 #define CONFIG_SYS_BAUDRATE_TABLE \ 122 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 123 124 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 125 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 126 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 127 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 128 129 /* I2C */ 130 #define CONFIG_SYS_I2C 131 #define CONFIG_SYS_I2C_FSL 132 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 133 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 134 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 135 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 136 137 /* 138 * RapidIO 139 */ 140 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 141 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 142 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 143 144 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 145 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 146 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 147 148 /* 149 * General PCI 150 * Memory space is mapped 1-1, but I/O space must start from 0. 151 */ 152 153 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 154 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 155 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 156 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 157 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 158 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 159 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 160 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 161 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 162 163 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 164 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 165 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 166 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 167 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 168 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 169 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 170 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 171 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 172 173 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 174 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 175 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 176 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 177 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 178 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 179 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 180 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 181 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 182 183 /* controller 4, Base address 203000 */ 184 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 185 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 186 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 187 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 188 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 189 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 190 191 #ifdef CONFIG_PCI 192 #define CONFIG_PCI_INDIRECT_BRIDGE 193 194 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 195 #endif /* CONFIG_PCI */ 196 197 /* SATA */ 198 #ifdef CONFIG_FSL_SATA_V2 199 #define CONFIG_SYS_SATA_MAX_DEVICE 2 200 #define CONFIG_SATA1 201 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 202 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 203 #define CONFIG_SATA2 204 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 205 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 206 207 #define CONFIG_LBA48 208 #endif 209 210 #ifdef CONFIG_FMAN_ENET 211 #define CONFIG_ETHPRIME "FM1@DTSEC1" 212 #endif 213 214 /* 215 * Environment 216 */ 217 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 218 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 219 220 /* 221 * Command line configuration. 222 */ 223 224 /* 225 * Miscellaneous configurable options 226 */ 227 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 228 229 /* 230 * For booting Linux, the board info and command line data 231 * have to be in the first 64 MB of memory, since this is 232 * the maximum mapped by the Linux kernel during initialization. 233 */ 234 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 235 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 236 237 #ifdef CONFIG_CMD_KGDB 238 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 239 #endif 240 241 /* 242 * Environment Configuration 243 */ 244 #define CONFIG_ROOTPATH "/opt/nfsroot" 245 #define CONFIG_BOOTFILE "uImage" 246 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 247 248 /* default location for tftp and bootm */ 249 #define CONFIG_LOADADDR 1000000 250 251 #define CONFIG_HVBOOT \ 252 "setenv bootargs config-addr=0x60000000; " \ 253 "bootm 0x01000000 - 0x00f00000" 254 255 #endif /* __CONFIG_H */ 256