1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __T4QDS_H 11 #define __T4QDS_H 12 13 #define CONFIG_CMD_REGINFO 14 15 /* High Level Configuration Options */ 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 22 #ifndef CONFIG_SYS_TEXT_BASE 23 #define CONFIG_SYS_TEXT_BASE 0xeff40000 24 #endif 25 26 #ifndef CONFIG_RESET_VECTOR_ADDRESS 27 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 28 #endif 29 30 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 31 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 32 #define CONFIG_FSL_IFC /* Enable IFC Support */ 33 #define CONFIG_PCI /* Enable PCI/PCIE */ 34 #define CONFIG_PCIE1 /* PCIE controller 1 */ 35 #define CONFIG_PCIE2 /* PCIE controller 2 */ 36 #define CONFIG_PCIE3 /* PCIE controller 3 */ 37 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 38 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 39 40 #define CONFIG_SYS_SRIO 41 #define CONFIG_SRIO1 /* SRIO port 1 */ 42 #define CONFIG_SRIO2 /* SRIO port 2 */ 43 44 #define CONFIG_FSL_LAW /* Use common FSL init code */ 45 46 #define CONFIG_ENV_OVERWRITE 47 48 /* 49 * These can be toggled for performance analysis, otherwise use default. 50 */ 51 #define CONFIG_SYS_CACHE_STASHING 52 #define CONFIG_BTB /* toggle branch predition */ 53 #ifdef CONFIG_DDR_ECC 54 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 55 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 56 #endif 57 58 #define CONFIG_ENABLE_36BIT_PHYS 59 60 #define CONFIG_ADDR_MAP 61 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 62 63 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 64 #define CONFIG_SYS_MEMTEST_END 0x00400000 65 #define CONFIG_SYS_ALT_MEMTEST 66 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 67 68 /* 69 * Config the L3 Cache as L3 SRAM 70 */ 71 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 72 #define CONFIG_SYS_L3_SIZE (512 << 10) 73 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 74 #ifdef CONFIG_RAMBOOT_PBL 75 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 76 #endif 77 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 78 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 79 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 80 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 81 82 #define CONFIG_SYS_DCSRBAR 0xf0000000 83 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 84 85 /* 86 * DDR Setup 87 */ 88 #define CONFIG_VERY_BIG_RAM 89 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 90 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 91 92 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 93 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 94 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 95 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 96 97 #define CONFIG_DDR_SPD 98 #define CONFIG_SYS_FSL_DDR3 99 100 /* 101 * IFC Definitions 102 */ 103 #define CONFIG_SYS_FLASH_BASE 0xe0000000 104 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 105 106 #ifdef CONFIG_SPL_BUILD 107 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 108 #else 109 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 110 #endif 111 112 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 113 #define CONFIG_MISC_INIT_R 114 115 #define CONFIG_HWCONFIG 116 117 /* define to use L1 as initial stack */ 118 #define CONFIG_L1_INIT_RAM 119 #define CONFIG_SYS_INIT_RAM_LOCK 120 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 121 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 122 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 123 /* The assembler doesn't like typecast */ 124 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 125 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 126 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 127 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 128 129 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 130 GENERATED_GBL_DATA_SIZE) 131 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 132 133 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 134 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 135 136 /* Serial Port - controlled on board with jumper J8 137 * open - index 2 138 * shorted - index 1 139 */ 140 #define CONFIG_CONS_INDEX 1 141 #define CONFIG_SYS_NS16550_SERIAL 142 #define CONFIG_SYS_NS16550_REG_SIZE 1 143 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 144 145 #define CONFIG_SYS_BAUDRATE_TABLE \ 146 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 147 148 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 149 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 150 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 151 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 152 153 /* I2C */ 154 #define CONFIG_SYS_I2C 155 #define CONFIG_SYS_I2C_FSL 156 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 157 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 158 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 159 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 160 161 /* 162 * RapidIO 163 */ 164 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 165 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 166 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 167 168 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 169 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 170 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 171 172 /* 173 * General PCI 174 * Memory space is mapped 1-1, but I/O space must start from 0. 175 */ 176 177 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 178 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 179 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 180 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 181 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 182 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 183 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 184 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 185 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 186 187 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 188 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 189 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 190 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 191 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 192 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 193 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 194 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 195 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 196 197 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 198 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 199 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 200 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 201 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 202 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 203 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 204 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 205 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 206 207 /* controller 4, Base address 203000 */ 208 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 209 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 210 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 211 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 212 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 213 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 214 215 #ifdef CONFIG_PCI 216 #define CONFIG_PCI_INDIRECT_BRIDGE 217 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 218 219 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 220 #define CONFIG_DOS_PARTITION 221 #endif /* CONFIG_PCI */ 222 223 /* SATA */ 224 #ifdef CONFIG_FSL_SATA_V2 225 #define CONFIG_LIBATA 226 #define CONFIG_FSL_SATA 227 228 #define CONFIG_SYS_SATA_MAX_DEVICE 2 229 #define CONFIG_SATA1 230 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 231 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 232 #define CONFIG_SATA2 233 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 234 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 235 236 #define CONFIG_LBA48 237 #define CONFIG_CMD_SATA 238 #define CONFIG_DOS_PARTITION 239 #endif 240 241 #ifdef CONFIG_FMAN_ENET 242 #define CONFIG_MII /* MII PHY management */ 243 #define CONFIG_ETHPRIME "FM1@DTSEC1" 244 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 245 #endif 246 247 /* 248 * Environment 249 */ 250 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 251 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 252 253 /* 254 * Command line configuration. 255 */ 256 #define CONFIG_CMD_ERRATA 257 #define CONFIG_CMD_IRQ 258 259 #ifdef CONFIG_PCI 260 #define CONFIG_CMD_PCI 261 #endif 262 263 /* 264 * Miscellaneous configurable options 265 */ 266 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 267 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 268 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 269 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 270 #ifdef CONFIG_CMD_KGDB 271 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 272 #else 273 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 274 #endif 275 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 276 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 277 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 278 279 /* 280 * For booting Linux, the board info and command line data 281 * have to be in the first 64 MB of memory, since this is 282 * the maximum mapped by the Linux kernel during initialization. 283 */ 284 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 285 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 286 287 #ifdef CONFIG_CMD_KGDB 288 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 289 #endif 290 291 /* 292 * Environment Configuration 293 */ 294 #define CONFIG_ROOTPATH "/opt/nfsroot" 295 #define CONFIG_BOOTFILE "uImage" 296 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 297 298 /* default location for tftp and bootm */ 299 #define CONFIG_LOADADDR 1000000 300 301 #define CONFIG_BAUDRATE 115200 302 303 #define CONFIG_HVBOOT \ 304 "setenv bootargs config-addr=0x60000000; " \ 305 "bootm 0x01000000 - 0x00f00000" 306 307 #endif /* __CONFIG_H */ 308