1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __T4QDS_H 11 #define __T4QDS_H 12 13 #define CONFIG_CMD_REGINFO 14 15 /* High Level Configuration Options */ 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 22 #ifndef CONFIG_SYS_TEXT_BASE 23 #define CONFIG_SYS_TEXT_BASE 0xeff40000 24 #endif 25 26 #ifndef CONFIG_RESET_VECTOR_ADDRESS 27 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 28 #endif 29 30 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 31 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 32 #define CONFIG_FSL_IFC /* Enable IFC Support */ 33 #define CONFIG_PCIE1 /* PCIE controller 1 */ 34 #define CONFIG_PCIE2 /* PCIE controller 2 */ 35 #define CONFIG_PCIE3 /* PCIE controller 3 */ 36 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 37 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 38 39 #define CONFIG_SYS_SRIO 40 #define CONFIG_SRIO1 /* SRIO port 1 */ 41 #define CONFIG_SRIO2 /* SRIO port 2 */ 42 43 #define CONFIG_FSL_LAW /* Use common FSL init code */ 44 45 #define CONFIG_ENV_OVERWRITE 46 47 /* 48 * These can be toggled for performance analysis, otherwise use default. 49 */ 50 #define CONFIG_SYS_CACHE_STASHING 51 #define CONFIG_BTB /* toggle branch predition */ 52 #ifdef CONFIG_DDR_ECC 53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 54 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 55 #endif 56 57 #define CONFIG_ENABLE_36BIT_PHYS 58 59 #define CONFIG_ADDR_MAP 60 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 61 62 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 63 #define CONFIG_SYS_MEMTEST_END 0x00400000 64 #define CONFIG_SYS_ALT_MEMTEST 65 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 66 67 /* 68 * Config the L3 Cache as L3 SRAM 69 */ 70 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 71 #define CONFIG_SYS_L3_SIZE (512 << 10) 72 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 73 #ifdef CONFIG_RAMBOOT_PBL 74 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 75 #endif 76 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 77 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 78 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 79 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 80 81 #define CONFIG_SYS_DCSRBAR 0xf0000000 82 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 83 84 /* 85 * DDR Setup 86 */ 87 #define CONFIG_VERY_BIG_RAM 88 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 89 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 90 91 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 92 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 93 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 94 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 95 96 #define CONFIG_DDR_SPD 97 #define CONFIG_SYS_FSL_DDR3 98 99 /* 100 * IFC Definitions 101 */ 102 #define CONFIG_SYS_FLASH_BASE 0xe0000000 103 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 104 105 #ifdef CONFIG_SPL_BUILD 106 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 107 #else 108 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 109 #endif 110 111 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 112 #define CONFIG_MISC_INIT_R 113 114 #define CONFIG_HWCONFIG 115 116 /* define to use L1 as initial stack */ 117 #define CONFIG_L1_INIT_RAM 118 #define CONFIG_SYS_INIT_RAM_LOCK 119 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 120 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 121 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 122 /* The assembler doesn't like typecast */ 123 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 124 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 125 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 126 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 127 128 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 129 GENERATED_GBL_DATA_SIZE) 130 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 131 132 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 133 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 134 135 /* Serial Port - controlled on board with jumper J8 136 * open - index 2 137 * shorted - index 1 138 */ 139 #define CONFIG_CONS_INDEX 1 140 #define CONFIG_SYS_NS16550_SERIAL 141 #define CONFIG_SYS_NS16550_REG_SIZE 1 142 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 143 144 #define CONFIG_SYS_BAUDRATE_TABLE \ 145 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 146 147 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 148 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 149 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 150 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 151 152 /* I2C */ 153 #define CONFIG_SYS_I2C 154 #define CONFIG_SYS_I2C_FSL 155 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 156 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 157 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 158 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 159 160 /* 161 * RapidIO 162 */ 163 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 164 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 165 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 166 167 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 168 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 169 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 170 171 /* 172 * General PCI 173 * Memory space is mapped 1-1, but I/O space must start from 0. 174 */ 175 176 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 177 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 178 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 179 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 180 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 181 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 182 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 183 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 184 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 185 186 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 187 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 188 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 189 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 190 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 191 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 192 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 193 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 194 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 195 196 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 197 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 198 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 199 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 200 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 201 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 202 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 203 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 204 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 205 206 /* controller 4, Base address 203000 */ 207 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 208 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 209 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 210 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 211 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 212 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 213 214 #ifdef CONFIG_PCI 215 #define CONFIG_PCI_INDIRECT_BRIDGE 216 217 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 218 #define CONFIG_DOS_PARTITION 219 #endif /* CONFIG_PCI */ 220 221 /* SATA */ 222 #ifdef CONFIG_FSL_SATA_V2 223 #define CONFIG_LIBATA 224 #define CONFIG_FSL_SATA 225 226 #define CONFIG_SYS_SATA_MAX_DEVICE 2 227 #define CONFIG_SATA1 228 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 229 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 230 #define CONFIG_SATA2 231 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 232 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 233 234 #define CONFIG_LBA48 235 #define CONFIG_CMD_SATA 236 #define CONFIG_DOS_PARTITION 237 #endif 238 239 #ifdef CONFIG_FMAN_ENET 240 #define CONFIG_MII /* MII PHY management */ 241 #define CONFIG_ETHPRIME "FM1@DTSEC1" 242 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 243 #endif 244 245 /* 246 * Environment 247 */ 248 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 249 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 250 251 /* 252 * Command line configuration. 253 */ 254 #define CONFIG_CMD_ERRATA 255 #define CONFIG_CMD_IRQ 256 257 #ifdef CONFIG_PCI 258 #define CONFIG_CMD_PCI 259 #endif 260 261 /* 262 * Miscellaneous configurable options 263 */ 264 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 265 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 266 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 267 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 268 #ifdef CONFIG_CMD_KGDB 269 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 270 #else 271 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 272 #endif 273 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 274 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 275 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 276 277 /* 278 * For booting Linux, the board info and command line data 279 * have to be in the first 64 MB of memory, since this is 280 * the maximum mapped by the Linux kernel during initialization. 281 */ 282 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 283 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 284 285 #ifdef CONFIG_CMD_KGDB 286 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 287 #endif 288 289 /* 290 * Environment Configuration 291 */ 292 #define CONFIG_ROOTPATH "/opt/nfsroot" 293 #define CONFIG_BOOTFILE "uImage" 294 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 295 296 /* default location for tftp and bootm */ 297 #define CONFIG_LOADADDR 1000000 298 299 #define CONFIG_BAUDRATE 115200 300 301 #define CONFIG_HVBOOT \ 302 "setenv bootargs config-addr=0x60000000; " \ 303 "bootm 0x01000000 - 0x00f00000" 304 305 #endif /* __CONFIG_H */ 306