1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * Corenet DS style board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #ifdef CONFIG_RAMBOOT_PBL 30 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 31 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 32 #endif 33 34 #define CONFIG_CMD_REGINFO 35 36 /* High Level Configuration Options */ 37 #define CONFIG_BOOKE 38 #define CONFIG_E6500 39 #define CONFIG_E500 /* BOOKE e500 family */ 40 #define CONFIG_E500MC /* BOOKE e500mc family */ 41 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 42 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 43 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 44 #define CONFIG_MP /* support multiple processors */ 45 46 #ifndef CONFIG_SYS_TEXT_BASE 47 #define CONFIG_SYS_TEXT_BASE 0xeff80000 48 #endif 49 50 #ifndef CONFIG_RESET_VECTOR_ADDRESS 51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 52 #endif 53 54 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 55 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 56 #define CONFIG_FSL_IFC /* Enable IFC Support */ 57 #define CONFIG_PCI /* Enable PCI/PCIE */ 58 #define CONFIG_PCIE1 /* PCIE controler 1 */ 59 #define CONFIG_PCIE2 /* PCIE controler 2 */ 60 #define CONFIG_PCIE3 /* PCIE controler 3 */ 61 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 62 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 63 64 #define CONFIG_SYS_SRIO 65 #define CONFIG_SRIO1 /* SRIO port 1 */ 66 #define CONFIG_SRIO2 /* SRIO port 2 */ 67 68 #define CONFIG_FSL_LAW /* Use common FSL init code */ 69 70 #define CONFIG_ENV_OVERWRITE 71 72 #ifdef CONFIG_SYS_NO_FLASH 73 #define CONFIG_ENV_IS_NOWHERE 74 #else 75 #define CONFIG_FLASH_CFI_DRIVER 76 #define CONFIG_SYS_FLASH_CFI 77 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 78 #endif 79 80 #ifndef CONFIG_SYS_NO_FLASH 81 #if defined(CONFIG_SPIFLASH) 82 #define CONFIG_SYS_EXTRA_ENV_RELOC 83 #define CONFIG_ENV_IS_IN_SPI_FLASH 84 #define CONFIG_ENV_SPI_BUS 0 85 #define CONFIG_ENV_SPI_CS 0 86 #define CONFIG_ENV_SPI_MAX_HZ 10000000 87 #define CONFIG_ENV_SPI_MODE 0 88 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 89 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 90 #define CONFIG_ENV_SECT_SIZE 0x10000 91 #elif defined(CONFIG_SDCARD) 92 #define CONFIG_SYS_EXTRA_ENV_RELOC 93 #define CONFIG_ENV_IS_IN_MMC 94 #define CONFIG_SYS_MMC_ENV_DEV 0 95 #define CONFIG_ENV_SIZE 0x2000 96 #define CONFIG_ENV_OFFSET (512 * 1097) 97 #elif defined(CONFIG_NAND) 98 #define CONFIG_SYS_EXTRA_ENV_RELOC 99 #define CONFIG_ENV_IS_IN_NAND 100 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 101 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 102 #else 103 #define CONFIG_ENV_IS_IN_FLASH 104 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 105 #define CONFIG_ENV_SIZE 0x2000 106 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 107 #endif 108 #else /* CONFIG_SYS_NO_FLASH */ 109 #define CONFIG_ENV_SIZE 0x2000 110 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 111 #endif 112 113 114 115 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 116 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 117 118 #ifndef __ASSEMBLY__ 119 unsigned long get_board_sys_clk(void); 120 unsigned long get_board_ddr_clk(void); 121 #endif 122 123 /* 124 * These can be toggled for performance analysis, otherwise use default. 125 */ 126 #define CONFIG_SYS_CACHE_STASHING 127 #define CONFIG_BTB /* toggle branch predition */ 128 #define CONFIG_DDR_ECC 129 #ifdef CONFIG_DDR_ECC 130 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 131 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 132 #endif 133 134 #define CONFIG_ENABLE_36BIT_PHYS 135 136 #ifdef CONFIG_PHYS_64BIT 137 #define CONFIG_ADDR_MAP 138 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 139 #endif 140 141 #if 0 142 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 143 #endif 144 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 145 #define CONFIG_SYS_MEMTEST_END 0x00400000 146 #define CONFIG_SYS_ALT_MEMTEST 147 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 148 149 /* 150 * Config the L3 Cache as L3 SRAM 151 */ 152 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 153 154 #ifdef CONFIG_PHYS_64BIT 155 #define CONFIG_SYS_DCSRBAR 0xf0000000 156 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 157 #endif 158 159 /* EEPROM */ 160 #define CONFIG_ID_EEPROM 161 #define CONFIG_SYS_I2C_EEPROM_NXID 162 #define CONFIG_SYS_EEPROM_BUS_NUM 0 163 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 164 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 165 166 /* 167 * DDR Setup 168 */ 169 #define CONFIG_VERY_BIG_RAM 170 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 171 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 172 173 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 174 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 175 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 176 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 177 178 #define CONFIG_DDR_SPD 179 #define CONFIG_FSL_DDR3 180 181 #define CONFIG_SYS_SPD_BUS_NUM 0 182 #define SPD_EEPROM_ADDRESS1 0x51 183 #define SPD_EEPROM_ADDRESS2 0x52 184 #define SPD_EEPROM_ADDRESS3 0x53 185 #define SPD_EEPROM_ADDRESS4 0x54 186 #define SPD_EEPROM_ADDRESS5 0x55 187 #define SPD_EEPROM_ADDRESS6 0x56 188 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 189 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 190 191 /* 192 * IFC Definitions 193 */ 194 #define CONFIG_SYS_FLASH_BASE 0xe0000000 195 #ifdef CONFIG_PHYS_64BIT 196 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 197 #else 198 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 199 #endif 200 201 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 202 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 203 + 0x8000000) | \ 204 CSPR_PORT_SIZE_16 | \ 205 CSPR_MSEL_NOR | \ 206 CSPR_V) 207 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 208 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 209 CSPR_PORT_SIZE_16 | \ 210 CSPR_MSEL_NOR | \ 211 CSPR_V) 212 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 213 /* NOR Flash Timing Params */ 214 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 215 216 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 217 FTIM0_NOR_TEADC(0x01) | \ 218 FTIM0_NOR_TEAHC(0x20)) 219 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 220 FTIM1_NOR_TRAD_NOR(0x1A) |\ 221 FTIM1_NOR_TSEQRAD_NOR(0x13)) 222 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 223 FTIM2_NOR_TCH(0x0E) | \ 224 FTIM2_NOR_TWPH(0x0E) | \ 225 FTIM2_NOR_TWP(0x1c)) 226 #define CONFIG_SYS_NOR_FTIM3 0x0 227 228 #define CONFIG_SYS_FLASH_QUIET_TEST 229 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 230 231 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 232 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 233 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 234 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 235 236 #define CONFIG_SYS_FLASH_EMPTY_INFO 237 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 238 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 239 240 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 241 #define QIXIS_BASE 0xffdf0000 242 #define QIXIS_LBMAP_SWITCH 6 243 #define QIXIS_LBMAP_MASK 0x0f 244 #define QIXIS_LBMAP_SHIFT 0 245 #define QIXIS_LBMAP_DFLTBANK 0x00 246 #define QIXIS_LBMAP_ALTBANK 0x04 247 #define QIXIS_RST_CTL_RESET 0x83 248 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 249 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 250 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 251 #ifdef CONFIG_PHYS_64BIT 252 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 253 #else 254 #define QIXIS_BASE_PHYS QIXIS_BASE 255 #endif 256 257 #define CONFIG_SYS_CSPR3_EXT (0xf) 258 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 259 | CSPR_PORT_SIZE_8 \ 260 | CSPR_MSEL_GPCM \ 261 | CSPR_V) 262 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 263 #define CONFIG_SYS_CSOR3 0x0 264 /* QIXIS Timing parameters for IFC CS3 */ 265 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 266 FTIM0_GPCM_TEADC(0x0e) | \ 267 FTIM0_GPCM_TEAHC(0x0e)) 268 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 269 FTIM1_GPCM_TRAD(0x3f)) 270 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 271 FTIM2_GPCM_TCH(0x0) | \ 272 FTIM2_GPCM_TWP(0x1f)) 273 #define CONFIG_SYS_CS3_FTIM3 0x0 274 275 /* NAND Flash on IFC */ 276 #define CONFIG_NAND_FSL_IFC 277 #define CONFIG_SYS_NAND_BASE 0xff800000 278 #ifdef CONFIG_PHYS_64BIT 279 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 280 #else 281 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 282 #endif 283 284 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 285 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 286 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 287 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 288 | CSPR_V) 289 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 290 291 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 292 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 293 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 294 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 295 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 296 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 297 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 298 299 #define CONFIG_SYS_NAND_ONFI_DETECTION 300 301 /* ONFI NAND Flash mode0 Timing Params */ 302 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 303 FTIM0_NAND_TWP(0x18) | \ 304 FTIM0_NAND_TWCHT(0x07) | \ 305 FTIM0_NAND_TWH(0x0a)) 306 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 307 FTIM1_NAND_TWBE(0x39) | \ 308 FTIM1_NAND_TRR(0x0e) | \ 309 FTIM1_NAND_TRP(0x18)) 310 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 311 FTIM2_NAND_TREH(0x0a) | \ 312 FTIM2_NAND_TWHRE(0x1e)) 313 #define CONFIG_SYS_NAND_FTIM3 0x0 314 315 #define CONFIG_SYS_NAND_DDR_LAW 11 316 317 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 318 #define CONFIG_SYS_MAX_NAND_DEVICE 1 319 #define CONFIG_MTD_NAND_VERIFY_WRITE 320 #define CONFIG_CMD_NAND 321 322 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 323 324 #if defined(CONFIG_NAND) 325 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 326 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 327 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 328 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 329 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 330 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 331 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 332 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 333 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 334 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 335 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 336 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 337 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 338 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 339 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 340 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 341 #else 342 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 343 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 344 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 345 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 346 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 347 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 348 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 349 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 350 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 351 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 352 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 353 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 354 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 355 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 356 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 357 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 358 #endif 359 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 360 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 361 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 362 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 363 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 364 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 365 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 366 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 367 368 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 369 370 #if defined(CONFIG_RAMBOOT_PBL) 371 #define CONFIG_SYS_RAMBOOT 372 #endif 373 374 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 375 #define CONFIG_MISC_INIT_R 376 377 #define CONFIG_HWCONFIG 378 379 /* define to use L1 as initial stack */ 380 #define CONFIG_L1_INIT_RAM 381 #define CONFIG_SYS_INIT_RAM_LOCK 382 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 383 #ifdef CONFIG_PHYS_64BIT 384 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 385 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 386 /* The assembler doesn't like typecast */ 387 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 388 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 389 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 390 #else 391 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 392 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 393 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 394 #endif 395 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 396 397 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 398 GENERATED_GBL_DATA_SIZE) 399 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 400 401 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 402 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 403 404 /* Serial Port - controlled on board with jumper J8 405 * open - index 2 406 * shorted - index 1 407 */ 408 #define CONFIG_CONS_INDEX 1 409 #define CONFIG_SYS_NS16550 410 #define CONFIG_SYS_NS16550_SERIAL 411 #define CONFIG_SYS_NS16550_REG_SIZE 1 412 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 413 414 #define CONFIG_SYS_BAUDRATE_TABLE \ 415 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 416 417 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 418 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 419 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 420 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 421 422 /* Use the HUSH parser */ 423 #define CONFIG_SYS_HUSH_PARSER 424 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 425 426 /* pass open firmware flat tree */ 427 #define CONFIG_OF_LIBFDT 428 #define CONFIG_OF_BOARD_SETUP 429 #define CONFIG_OF_STDOUT_VIA_ALIAS 430 431 /* new uImage format support */ 432 #define CONFIG_FIT 433 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 434 435 /* I2C */ 436 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 437 #define CONFIG_HARD_I2C /* I2C with hardware support */ 438 #define CONFIG_I2C_MULTI_BUS 439 #define CONFIG_I2C_CMD_TREE 440 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ 441 #define CONFIG_SYS_I2C_SLAVE 0x7F 442 #define CONFIG_SYS_I2C_OFFSET 0x118000 443 #define CONFIG_SYS_I2C2_OFFSET 0x118100 444 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 445 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 446 447 /* VSC Crossbar switches */ 448 #define CONFIG_VSC_CROSSBAR 449 #define I2C_MUX_CH_DEFAULT 0x8 450 #define I2C_MUX_CH_VSC3316_FS 0xc 451 #define I2C_MUX_CH_VSC3316_BS 0xd 452 #define VSC3316_FSM_TX_ADDR 0x70 453 #define VSC3316_FSM_RX_ADDR 0x71 454 455 /* 456 * RapidIO 457 */ 458 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 459 #ifdef CONFIG_PHYS_64BIT 460 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 461 #else 462 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 463 #endif 464 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 465 466 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 467 #ifdef CONFIG_PHYS_64BIT 468 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 469 #else 470 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 471 #endif 472 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 473 474 /* 475 * for slave u-boot IMAGE instored in master memory space, 476 * PHYS must be aligned based on the SIZE 477 */ 478 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 479 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 480 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 481 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 482 /* 483 * for slave UCODE and ENV instored in master memory space, 484 * PHYS must be aligned based on the SIZE 485 */ 486 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 487 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 488 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 489 490 /* slave core release by master*/ 491 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 492 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 493 494 /* 495 * SRIO_PCIE_BOOT - SLAVE 496 */ 497 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 498 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 499 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 500 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 501 #endif 502 /* 503 * eSPI - Enhanced SPI 504 */ 505 #define CONFIG_FSL_ESPI 506 #define CONFIG_SPI_FLASH 507 #define CONFIG_SPI_FLASH_SPANSION 508 #define CONFIG_CMD_SF 509 #define CONFIG_SF_DEFAULT_SPEED 10000000 510 #define CONFIG_SF_DEFAULT_MODE 0 511 512 /* 513 * General PCI 514 * Memory space is mapped 1-1, but I/O space must start from 0. 515 */ 516 517 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 518 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 519 #ifdef CONFIG_PHYS_64BIT 520 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 521 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 522 #else 523 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 524 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 525 #endif 526 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 527 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 528 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 529 #ifdef CONFIG_PHYS_64BIT 530 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 531 #else 532 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 533 #endif 534 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 535 536 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 537 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 538 #ifdef CONFIG_PHYS_64BIT 539 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 540 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 541 #else 542 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 543 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 544 #endif 545 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 546 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 547 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 548 #ifdef CONFIG_PHYS_64BIT 549 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 550 #else 551 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 552 #endif 553 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 554 555 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 556 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 557 #ifdef CONFIG_PHYS_64BIT 558 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 559 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 560 #else 561 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 562 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 563 #endif 564 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 565 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 566 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 567 #ifdef CONFIG_PHYS_64BIT 568 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 569 #else 570 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 571 #endif 572 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 573 574 /* controller 4, Base address 203000 */ 575 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 576 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 577 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 578 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 579 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 580 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 581 582 /* Qman/Bman */ 583 #ifndef CONFIG_NOBQFMAN 584 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 585 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 586 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 587 #ifdef CONFIG_PHYS_64BIT 588 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 589 #else 590 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 591 #endif 592 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 593 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 594 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 595 #ifdef CONFIG_PHYS_64BIT 596 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 597 #else 598 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 599 #endif 600 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 601 602 #define CONFIG_SYS_DPAA_FMAN 603 #define CONFIG_SYS_DPAA_PME 604 #define CONFIG_SYS_PMAN 605 #define CONFIG_SYS_DPAA_DCE 606 #define CONFIG_SYS_INTERLAKEN 607 608 /* Default address of microcode for the Linux Fman driver */ 609 #if defined(CONFIG_SPIFLASH) 610 /* 611 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 612 * env, so we got 0x110000. 613 */ 614 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 615 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 616 #elif defined(CONFIG_SDCARD) 617 /* 618 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 619 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 620 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 621 */ 622 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 623 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 624 #elif defined(CONFIG_NAND) 625 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 626 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 627 #else 628 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 629 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 630 #endif 631 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 632 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 633 #endif /* CONFIG_NOBQFMAN */ 634 635 #ifdef CONFIG_SYS_DPAA_FMAN 636 #define CONFIG_FMAN_ENET 637 #define CONFIG_PHYLIB_10G 638 #define CONFIG_PHY_VITESSE 639 #define CONFIG_PHY_TERANETICS 640 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 641 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 642 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 643 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 644 #define XFI_CARD_PORT1_PHY_ADDR 0x1 /* tmp, FIXME below addr */ 645 #define XFI_CARD_PORT2_PHY_ADDR 0x2 646 #define XFI_CARD_PORT3_PHY_ADDR 0x3 647 #define XFI_CARD_PORT4_PHY_ADDR 0x4 648 #define QSGMII_CARD_PHY_ADDR 0x5 649 #define FM1_10GEC1_PHY_ADDR 0x6 650 #define FM1_10GEC2_PHY_ADDR 0x7 651 #define FM2_10GEC1_PHY_ADDR 0x8 652 #define FM2_10GEC2_PHY_ADDR 0x9 653 #endif 654 655 #ifdef CONFIG_PCI 656 #define CONFIG_NET_MULTI 657 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 658 #define CONFIG_E1000 659 660 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 661 #define CONFIG_DOS_PARTITION 662 #endif /* CONFIG_PCI */ 663 664 /* SATA */ 665 #ifdef CONFIG_FSL_SATA_V2 666 #define CONFIG_LIBATA 667 #define CONFIG_FSL_SATA 668 669 #define CONFIG_SYS_SATA_MAX_DEVICE 2 670 #define CONFIG_SATA1 671 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 672 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 673 #define CONFIG_SATA2 674 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 675 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 676 677 #define CONFIG_LBA48 678 #define CONFIG_CMD_SATA 679 #define CONFIG_DOS_PARTITION 680 #define CONFIG_CMD_EXT2 681 #endif 682 683 #ifdef CONFIG_FMAN_ENET 684 #define CONFIG_MII /* MII PHY management */ 685 #define CONFIG_ETHPRIME "FM1@DTSEC1" 686 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 687 #endif 688 689 /* 690 * Environment 691 */ 692 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 693 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 694 695 /* 696 * Command line configuration. 697 */ 698 #include <config_cmd_default.h> 699 700 #define CONFIG_CMD_DHCP 701 #define CONFIG_CMD_ELF 702 #define CONFIG_CMD_ERRATA 703 #define CONFIG_CMD_GREPENV 704 #define CONFIG_CMD_IRQ 705 #define CONFIG_CMD_I2C 706 #define CONFIG_CMD_MII 707 #define CONFIG_CMD_PING 708 #define CONFIG_CMD_SETEXPR 709 710 #ifdef CONFIG_PCI 711 #define CONFIG_CMD_PCI 712 #define CONFIG_CMD_NET 713 #endif 714 715 /* 716 * USB 717 */ 718 #define CONFIG_CMD_USB 719 #define CONFIG_USB_STORAGE 720 #define CONFIG_USB_EHCI 721 #define CONFIG_USB_EHCI_FSL 722 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 723 #define CONFIG_CMD_EXT2 724 #define CONFIG_HAS_FSL_DR_USB 725 726 #define CONFIG_MMC 727 728 #ifdef CONFIG_MMC 729 #define CONFIG_FSL_ESDHC 730 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 731 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 732 #define CONFIG_CMD_MMC 733 #define CONFIG_GENERIC_MMC 734 #define CONFIG_CMD_EXT2 735 #define CONFIG_CMD_FAT 736 #define CONFIG_DOS_PARTITION 737 #endif 738 739 /* 740 * Miscellaneous configurable options 741 */ 742 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 743 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 744 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 745 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 746 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 747 #ifdef CONFIG_CMD_KGDB 748 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 749 #else 750 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 751 #endif 752 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 753 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 754 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 755 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ 756 757 /* 758 * For booting Linux, the board info and command line data 759 * have to be in the first 64 MB of memory, since this is 760 * the maximum mapped by the Linux kernel during initialization. 761 */ 762 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 763 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 764 765 #ifdef CONFIG_CMD_KGDB 766 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 767 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 768 #endif 769 770 /* 771 * Environment Configuration 772 */ 773 #define CONFIG_ROOTPATH "/opt/nfsroot" 774 #define CONFIG_BOOTFILE "uImage" 775 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 776 777 /* default location for tftp and bootm */ 778 #define CONFIG_LOADADDR 1000000 779 780 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 781 782 #define CONFIG_BAUDRATE 115200 783 784 #define __USB_PHY_TYPE utmi 785 786 #define CONFIG_EXTRA_ENV_SETTINGS \ 787 "hwconfig=fsl_ddr:ctlr_intlv=3way_4KB," \ 788 "bank_intlv=auto;" \ 789 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 790 "netdev=eth0\0" \ 791 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 792 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 793 "tftpflash=tftpboot $loadaddr $uboot && " \ 794 "protect off $ubootaddr +$filesize && " \ 795 "erase $ubootaddr +$filesize && " \ 796 "cp.b $loadaddr $ubootaddr $filesize && " \ 797 "protect on $ubootaddr +$filesize && " \ 798 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 799 "consoledev=ttyS0\0" \ 800 "ramdiskaddr=2000000\0" \ 801 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 802 "fdtaddr=c00000\0" \ 803 "fdtfile=t4240qds/t4240qds.dtb\0" \ 804 "bdev=sda3\0" \ 805 "c=ffe\0" 806 807 /* For emulation this causes u-boot to jump to the start of the proof point 808 app code automatically */ 809 #define CONFIG_PROOF_POINTS \ 810 "setenv bootargs root=/dev/$bdev rw " \ 811 "console=$consoledev,$baudrate $othbootargs;" \ 812 "cpu 1 release 0x29000000 - - -;" \ 813 "cpu 2 release 0x29000000 - - -;" \ 814 "cpu 3 release 0x29000000 - - -;" \ 815 "cpu 4 release 0x29000000 - - -;" \ 816 "cpu 5 release 0x29000000 - - -;" \ 817 "cpu 6 release 0x29000000 - - -;" \ 818 "cpu 7 release 0x29000000 - - -;" \ 819 "go 0x29000000" 820 821 #define CONFIG_HVBOOT \ 822 "setenv bootargs config-addr=0x60000000; " \ 823 "bootm 0x01000000 - 0x00f00000" 824 825 #define CONFIG_ALU \ 826 "setenv bootargs root=/dev/$bdev rw " \ 827 "console=$consoledev,$baudrate $othbootargs;" \ 828 "cpu 1 release 0x01000000 - - -;" \ 829 "cpu 2 release 0x01000000 - - -;" \ 830 "cpu 3 release 0x01000000 - - -;" \ 831 "cpu 4 release 0x01000000 - - -;" \ 832 "cpu 5 release 0x01000000 - - -;" \ 833 "cpu 6 release 0x01000000 - - -;" \ 834 "cpu 7 release 0x01000000 - - -;" \ 835 "go 0x01000000" 836 837 #define CONFIG_LINUX \ 838 "setenv bootargs root=/dev/ram rw " \ 839 "console=$consoledev,$baudrate $othbootargs;" \ 840 "setenv ramdiskaddr 0x02000000;" \ 841 "setenv fdtaddr 0x00c00000;" \ 842 "setenv loadaddr 0x1000000;" \ 843 "bootm $loadaddr $ramdiskaddr $fdtaddr" 844 845 #define CONFIG_HDBOOT \ 846 "setenv bootargs root=/dev/$bdev rw " \ 847 "console=$consoledev,$baudrate $othbootargs;" \ 848 "tftp $loadaddr $bootfile;" \ 849 "tftp $fdtaddr $fdtfile;" \ 850 "bootm $loadaddr - $fdtaddr" 851 852 #define CONFIG_NFSBOOTCOMMAND \ 853 "setenv bootargs root=/dev/nfs rw " \ 854 "nfsroot=$serverip:$rootpath " \ 855 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 856 "console=$consoledev,$baudrate $othbootargs;" \ 857 "tftp $loadaddr $bootfile;" \ 858 "tftp $fdtaddr $fdtfile;" \ 859 "bootm $loadaddr - $fdtaddr" 860 861 #define CONFIG_RAMBOOTCOMMAND \ 862 "setenv bootargs root=/dev/ram rw " \ 863 "console=$consoledev,$baudrate $othbootargs;" \ 864 "tftp $ramdiskaddr $ramdiskfile;" \ 865 "tftp $loadaddr $bootfile;" \ 866 "tftp $fdtaddr $fdtfile;" \ 867 "bootm $loadaddr $ramdiskaddr $fdtaddr" 868 869 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 870 871 #ifdef CONFIG_SECURE_BOOT 872 #include <asm/fsl_secure_boot.h> 873 #endif 874 875 #endif /* __CONFIG_H */ 876