1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * Corenet DS style board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #ifdef CONFIG_RAMBOOT_PBL 30 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 31 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 32 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg 33 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg 34 #endif 35 36 #define CONFIG_CMD_REGINFO 37 38 /* High Level Configuration Options */ 39 #define CONFIG_BOOKE 40 #define CONFIG_E500 /* BOOKE e500 family */ 41 #define CONFIG_E500MC /* BOOKE e500mc family */ 42 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 43 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 44 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 45 #define CONFIG_MP /* support multiple processors */ 46 47 #ifndef CONFIG_SYS_TEXT_BASE 48 #define CONFIG_SYS_TEXT_BASE 0xeff80000 49 #endif 50 51 #ifndef CONFIG_RESET_VECTOR_ADDRESS 52 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 53 #endif 54 55 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 56 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 57 #define CONFIG_FSL_IFC /* Enable IFC Support */ 58 #define CONFIG_PCI /* Enable PCI/PCIE */ 59 #define CONFIG_PCIE1 /* PCIE controler 1 */ 60 #define CONFIG_PCIE2 /* PCIE controler 2 */ 61 #define CONFIG_PCIE3 /* PCIE controler 3 */ 62 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 63 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 64 65 #define CONFIG_SYS_SRIO 66 #define CONFIG_SRIO1 /* SRIO port 1 */ 67 #define CONFIG_SRIO2 /* SRIO port 2 */ 68 #define CONFIG_SRIO_PCIE_BOOT_MASTER 69 70 #define CONFIG_FSL_LAW /* Use common FSL init code */ 71 72 #define CONFIG_ENV_OVERWRITE 73 74 #ifdef CONFIG_SYS_NO_FLASH 75 #define CONFIG_ENV_IS_NOWHERE 76 #else 77 #define CONFIG_FLASH_CFI_DRIVER 78 #define CONFIG_SYS_FLASH_CFI 79 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 80 #endif 81 82 #ifndef CONFIG_SYS_NO_FLASH 83 #if defined(CONFIG_SPIFLASH) 84 #define CONFIG_SYS_EXTRA_ENV_RELOC 85 #define CONFIG_ENV_IS_IN_SPI_FLASH 86 #define CONFIG_ENV_SPI_BUS 0 87 #define CONFIG_ENV_SPI_CS 0 88 #define CONFIG_ENV_SPI_MAX_HZ 10000000 89 #define CONFIG_ENV_SPI_MODE 0 90 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 91 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 92 #define CONFIG_ENV_SECT_SIZE 0x10000 93 #elif defined(CONFIG_SDCARD) 94 #define CONFIG_SYS_EXTRA_ENV_RELOC 95 #define CONFIG_ENV_IS_IN_MMC 96 #define CONFIG_SYS_MMC_ENV_DEV 0 97 #define CONFIG_ENV_SIZE 0x2000 98 #define CONFIG_ENV_OFFSET (512 * 1097) 99 #elif defined(CONFIG_NAND) 100 #define CONFIG_SYS_EXTRA_ENV_RELOC 101 #define CONFIG_ENV_IS_IN_NAND 102 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 103 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 104 #else 105 #define CONFIG_ENV_IS_IN_FLASH 106 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 107 #define CONFIG_ENV_SIZE 0x2000 108 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 109 #endif 110 #else /* CONFIG_SYS_NO_FLASH */ 111 #define CONFIG_ENV_SIZE 0x2000 112 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 113 #endif 114 115 116 117 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 118 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 119 120 #ifndef __ASSEMBLY__ 121 unsigned long get_board_sys_clk(void); 122 unsigned long get_board_ddr_clk(void); 123 #endif 124 125 /* 126 * These can be toggled for performance analysis, otherwise use default. 127 */ 128 #define CONFIG_SYS_CACHE_STASHING 129 #define CONFIG_BTB /* toggle branch predition */ 130 #define CONFIG_DDR_ECC 131 #ifdef CONFIG_DDR_ECC 132 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 133 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 134 #endif 135 136 #define CONFIG_ENABLE_36BIT_PHYS 137 138 #ifdef CONFIG_PHYS_64BIT 139 #define CONFIG_ADDR_MAP 140 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 141 #endif 142 143 #if 0 144 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 145 #endif 146 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 147 #define CONFIG_SYS_MEMTEST_END 0x00400000 148 #define CONFIG_SYS_ALT_MEMTEST 149 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 150 151 /* 152 * Config the L3 Cache as L3 SRAM 153 */ 154 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 155 156 #ifdef CONFIG_PHYS_64BIT 157 #define CONFIG_SYS_DCSRBAR 0xf0000000 158 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 159 #endif 160 161 /* EEPROM */ 162 #define CONFIG_ID_EEPROM 163 #define CONFIG_SYS_I2C_EEPROM_NXID 164 #define CONFIG_SYS_EEPROM_BUS_NUM 0 165 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 167 168 /* 169 * DDR Setup 170 */ 171 #define CONFIG_VERY_BIG_RAM 172 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 173 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 174 175 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 176 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 177 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 178 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 179 180 #define CONFIG_DDR_SPD 181 #define CONFIG_FSL_DDR3 182 183 #define CONFIG_SYS_SPD_BUS_NUM 0 184 #define SPD_EEPROM_ADDRESS1 0x51 185 #define SPD_EEPROM_ADDRESS2 0x52 186 #define SPD_EEPROM_ADDRESS3 0x53 187 #define SPD_EEPROM_ADDRESS4 0x54 188 #define SPD_EEPROM_ADDRESS5 0x55 189 #define SPD_EEPROM_ADDRESS6 0x56 190 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 191 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 192 193 /* 194 * IFC Definitions 195 */ 196 #define CONFIG_SYS_FLASH_BASE 0xe0000000 197 #ifdef CONFIG_PHYS_64BIT 198 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 199 #else 200 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 201 #endif 202 203 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 204 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 205 + 0x8000000) | \ 206 CSPR_PORT_SIZE_16 | \ 207 CSPR_MSEL_NOR | \ 208 CSPR_V) 209 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 210 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 211 CSPR_PORT_SIZE_16 | \ 212 CSPR_MSEL_NOR | \ 213 CSPR_V) 214 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 215 /* NOR Flash Timing Params */ 216 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 217 218 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 219 FTIM0_NOR_TEADC(0x5) | \ 220 FTIM0_NOR_TEAHC(0x5)) 221 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 222 FTIM1_NOR_TRAD_NOR(0x1A) |\ 223 FTIM1_NOR_TSEQRAD_NOR(0x13)) 224 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 225 FTIM2_NOR_TCH(0x4) | \ 226 FTIM2_NOR_TWPH(0x0E) | \ 227 FTIM2_NOR_TWP(0x1c)) 228 #define CONFIG_SYS_NOR_FTIM3 0x0 229 230 #define CONFIG_SYS_FLASH_QUIET_TEST 231 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 232 233 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 234 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 235 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 236 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 237 238 #define CONFIG_SYS_FLASH_EMPTY_INFO 239 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 240 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 241 242 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 243 #define QIXIS_BASE 0xffdf0000 244 #define QIXIS_LBMAP_SWITCH 6 245 #define QIXIS_LBMAP_MASK 0x0f 246 #define QIXIS_LBMAP_SHIFT 0 247 #define QIXIS_LBMAP_DFLTBANK 0x00 248 #define QIXIS_LBMAP_ALTBANK 0x04 249 #define QIXIS_RST_CTL_RESET 0x83 250 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 251 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 252 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 253 #ifdef CONFIG_PHYS_64BIT 254 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 255 #else 256 #define QIXIS_BASE_PHYS QIXIS_BASE 257 #endif 258 259 #define CONFIG_SYS_CSPR3_EXT (0xf) 260 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 261 | CSPR_PORT_SIZE_8 \ 262 | CSPR_MSEL_GPCM \ 263 | CSPR_V) 264 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 265 #define CONFIG_SYS_CSOR3 0x0 266 /* QIXIS Timing parameters for IFC CS3 */ 267 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 268 FTIM0_GPCM_TEADC(0x0e) | \ 269 FTIM0_GPCM_TEAHC(0x0e)) 270 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 271 FTIM1_GPCM_TRAD(0x3f)) 272 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 273 FTIM2_GPCM_TCH(0x0) | \ 274 FTIM2_GPCM_TWP(0x1f)) 275 #define CONFIG_SYS_CS3_FTIM3 0x0 276 277 /* NAND Flash on IFC */ 278 #define CONFIG_NAND_FSL_IFC 279 #define CONFIG_SYS_NAND_BASE 0xff800000 280 #ifdef CONFIG_PHYS_64BIT 281 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 282 #else 283 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 284 #endif 285 286 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 287 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 288 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 289 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 290 | CSPR_V) 291 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 292 293 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 294 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 295 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 296 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 297 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 298 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 299 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 300 301 #define CONFIG_SYS_NAND_ONFI_DETECTION 302 303 /* ONFI NAND Flash mode0 Timing Params */ 304 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 305 FTIM0_NAND_TWP(0x18) | \ 306 FTIM0_NAND_TWCHT(0x07) | \ 307 FTIM0_NAND_TWH(0x0a)) 308 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 309 FTIM1_NAND_TWBE(0x39) | \ 310 FTIM1_NAND_TRR(0x0e) | \ 311 FTIM1_NAND_TRP(0x18)) 312 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 313 FTIM2_NAND_TREH(0x0a) | \ 314 FTIM2_NAND_TWHRE(0x1e)) 315 #define CONFIG_SYS_NAND_FTIM3 0x0 316 317 #define CONFIG_SYS_NAND_DDR_LAW 11 318 319 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 320 #define CONFIG_SYS_MAX_NAND_DEVICE 1 321 #define CONFIG_MTD_NAND_VERIFY_WRITE 322 #define CONFIG_CMD_NAND 323 324 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 325 326 #if defined(CONFIG_NAND) 327 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 328 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 329 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 330 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 331 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 332 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 333 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 334 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 335 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 336 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 337 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 338 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 339 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 340 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 341 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 342 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 343 #else 344 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 345 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 346 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 347 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 348 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 349 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 350 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 351 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 352 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 353 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 354 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 355 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 356 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 357 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 358 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 359 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 360 #endif 361 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 362 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 363 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 364 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 365 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 366 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 367 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 368 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 369 370 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 371 372 #if defined(CONFIG_RAMBOOT_PBL) 373 #define CONFIG_SYS_RAMBOOT 374 #endif 375 376 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 377 #define CONFIG_MISC_INIT_R 378 379 #define CONFIG_HWCONFIG 380 381 /* define to use L1 as initial stack */ 382 #define CONFIG_L1_INIT_RAM 383 #define CONFIG_SYS_INIT_RAM_LOCK 384 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 385 #ifdef CONFIG_PHYS_64BIT 386 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 387 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 388 /* The assembler doesn't like typecast */ 389 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 390 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 391 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 392 #else 393 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 394 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 395 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 396 #endif 397 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 398 399 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 400 GENERATED_GBL_DATA_SIZE) 401 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 402 403 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 404 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 405 406 /* Serial Port - controlled on board with jumper J8 407 * open - index 2 408 * shorted - index 1 409 */ 410 #define CONFIG_CONS_INDEX 1 411 #define CONFIG_SYS_NS16550 412 #define CONFIG_SYS_NS16550_SERIAL 413 #define CONFIG_SYS_NS16550_REG_SIZE 1 414 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 415 416 #define CONFIG_SYS_BAUDRATE_TABLE \ 417 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 418 419 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 420 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 421 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 422 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 423 424 /* Use the HUSH parser */ 425 #define CONFIG_SYS_HUSH_PARSER 426 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 427 428 /* pass open firmware flat tree */ 429 #define CONFIG_OF_LIBFDT 430 #define CONFIG_OF_BOARD_SETUP 431 #define CONFIG_OF_STDOUT_VIA_ALIAS 432 433 /* new uImage format support */ 434 #define CONFIG_FIT 435 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 436 437 /* I2C */ 438 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 439 #define CONFIG_HARD_I2C /* I2C with hardware support */ 440 #define CONFIG_I2C_MULTI_BUS 441 #define CONFIG_I2C_CMD_TREE 442 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ 443 #define CONFIG_SYS_I2C_SLAVE 0x7F 444 #define CONFIG_SYS_I2C_OFFSET 0x118000 445 #define CONFIG_SYS_I2C2_OFFSET 0x118100 446 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 447 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 448 449 #define I2C_MUX_CH_DEFAULT 0x8 450 #define I2C_MUX_CH_VOL_MONITOR 0xa 451 #define I2C_MUX_CH_VSC3316_FS 0xc 452 #define I2C_MUX_CH_VSC3316_BS 0xd 453 454 /* Voltage monitor on channel 2*/ 455 #define I2C_VOL_MONITOR_ADDR 0x40 456 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 457 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 458 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 459 460 /* VSC Crossbar switches */ 461 #define CONFIG_VSC_CROSSBAR 462 #define VSC3316_FSM_TX_ADDR 0x70 463 #define VSC3316_FSM_RX_ADDR 0x71 464 465 /* 466 * RapidIO 467 */ 468 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 469 #ifdef CONFIG_PHYS_64BIT 470 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 471 #else 472 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 473 #endif 474 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 475 476 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 477 #ifdef CONFIG_PHYS_64BIT 478 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 479 #else 480 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 481 #endif 482 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 483 484 /* 485 * for slave u-boot IMAGE instored in master memory space, 486 * PHYS must be aligned based on the SIZE 487 */ 488 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 489 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 490 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 491 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 492 /* 493 * for slave UCODE and ENV instored in master memory space, 494 * PHYS must be aligned based on the SIZE 495 */ 496 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 497 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 498 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 499 500 /* slave core release by master*/ 501 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 502 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 503 504 /* 505 * SRIO_PCIE_BOOT - SLAVE 506 */ 507 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 508 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 509 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 510 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 511 #endif 512 /* 513 * eSPI - Enhanced SPI 514 */ 515 #define CONFIG_FSL_ESPI 516 #define CONFIG_SPI_FLASH 517 #define CONFIG_SPI_FLASH_SST 518 #define CONFIG_CMD_SF 519 #define CONFIG_SF_DEFAULT_SPEED 10000000 520 #define CONFIG_SF_DEFAULT_MODE 0 521 522 /* 523 * General PCI 524 * Memory space is mapped 1-1, but I/O space must start from 0. 525 */ 526 527 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 528 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 529 #ifdef CONFIG_PHYS_64BIT 530 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 531 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 532 #else 533 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 534 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 535 #endif 536 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 537 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 538 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 539 #ifdef CONFIG_PHYS_64BIT 540 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 541 #else 542 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 543 #endif 544 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 545 546 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 547 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 548 #ifdef CONFIG_PHYS_64BIT 549 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 550 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 551 #else 552 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 553 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 554 #endif 555 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 556 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 557 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 558 #ifdef CONFIG_PHYS_64BIT 559 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 560 #else 561 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 562 #endif 563 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 564 565 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 566 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 567 #ifdef CONFIG_PHYS_64BIT 568 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 569 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 570 #else 571 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 572 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 573 #endif 574 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 575 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 576 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 577 #ifdef CONFIG_PHYS_64BIT 578 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 579 #else 580 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 581 #endif 582 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 583 584 /* controller 4, Base address 203000 */ 585 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 586 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 587 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 588 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 589 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 590 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 591 592 /* Qman/Bman */ 593 #ifndef CONFIG_NOBQFMAN 594 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 595 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 596 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 597 #ifdef CONFIG_PHYS_64BIT 598 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 599 #else 600 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 601 #endif 602 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 603 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 604 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 605 #ifdef CONFIG_PHYS_64BIT 606 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 607 #else 608 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 609 #endif 610 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 611 612 #define CONFIG_SYS_DPAA_FMAN 613 #define CONFIG_SYS_DPAA_PME 614 #define CONFIG_SYS_PMAN 615 #define CONFIG_SYS_DPAA_DCE 616 #define CONFIG_SYS_INTERLAKEN 617 618 /* Default address of microcode for the Linux Fman driver */ 619 #if defined(CONFIG_SPIFLASH) 620 /* 621 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 622 * env, so we got 0x110000. 623 */ 624 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 625 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 626 #elif defined(CONFIG_SDCARD) 627 /* 628 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 629 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 630 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 631 */ 632 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 633 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 634 #elif defined(CONFIG_NAND) 635 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 636 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 637 #else 638 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 639 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 640 #endif 641 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 642 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 643 #endif /* CONFIG_NOBQFMAN */ 644 645 #ifdef CONFIG_SYS_DPAA_FMAN 646 #define CONFIG_FMAN_ENET 647 #define CONFIG_PHYLIB_10G 648 #define CONFIG_PHY_VITESSE 649 #define CONFIG_PHY_TERANETICS 650 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 651 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 652 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 653 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 654 #define FM1_10GEC1_PHY_ADDR 0x0 655 #define FM1_10GEC2_PHY_ADDR 0x1 656 #define FM2_10GEC1_PHY_ADDR 0x2 657 #define FM2_10GEC2_PHY_ADDR 0x3 658 #endif 659 660 #ifdef CONFIG_PCI 661 #define CONFIG_PCI_INDIRECT_BRIDGE 662 #define CONFIG_NET_MULTI 663 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 664 #define CONFIG_E1000 665 666 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 667 #define CONFIG_DOS_PARTITION 668 #endif /* CONFIG_PCI */ 669 670 /* SATA */ 671 #ifdef CONFIG_FSL_SATA_V2 672 #define CONFIG_LIBATA 673 #define CONFIG_FSL_SATA 674 675 #define CONFIG_SYS_SATA_MAX_DEVICE 2 676 #define CONFIG_SATA1 677 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 678 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 679 #define CONFIG_SATA2 680 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 681 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 682 683 #define CONFIG_LBA48 684 #define CONFIG_CMD_SATA 685 #define CONFIG_DOS_PARTITION 686 #define CONFIG_CMD_EXT2 687 #endif 688 689 #ifdef CONFIG_FMAN_ENET 690 #define CONFIG_MII /* MII PHY management */ 691 #define CONFIG_ETHPRIME "FM1@DTSEC1" 692 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 693 #endif 694 695 /* 696 * Environment 697 */ 698 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 699 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 700 701 /* 702 * Command line configuration. 703 */ 704 #include <config_cmd_default.h> 705 706 #define CONFIG_CMD_DHCP 707 #define CONFIG_CMD_ELF 708 #define CONFIG_CMD_ERRATA 709 #define CONFIG_CMD_GREPENV 710 #define CONFIG_CMD_IRQ 711 #define CONFIG_CMD_I2C 712 #define CONFIG_CMD_MII 713 #define CONFIG_CMD_PING 714 #define CONFIG_CMD_SETEXPR 715 716 #ifdef CONFIG_PCI 717 #define CONFIG_CMD_PCI 718 #define CONFIG_CMD_NET 719 #endif 720 721 /* 722 * USB 723 */ 724 #define CONFIG_CMD_USB 725 #define CONFIG_USB_STORAGE 726 #define CONFIG_USB_EHCI 727 #define CONFIG_USB_EHCI_FSL 728 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 729 #define CONFIG_CMD_EXT2 730 #define CONFIG_HAS_FSL_DR_USB 731 732 #define CONFIG_MMC 733 734 #ifdef CONFIG_MMC 735 #define CONFIG_FSL_ESDHC 736 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 737 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 738 #define CONFIG_CMD_MMC 739 #define CONFIG_GENERIC_MMC 740 #define CONFIG_CMD_EXT2 741 #define CONFIG_CMD_FAT 742 #define CONFIG_DOS_PARTITION 743 #endif 744 745 /* 746 * Miscellaneous configurable options 747 */ 748 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 749 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 750 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 751 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 752 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 753 #ifdef CONFIG_CMD_KGDB 754 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 755 #else 756 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 757 #endif 758 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 759 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 760 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 761 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ 762 763 /* 764 * For booting Linux, the board info and command line data 765 * have to be in the first 64 MB of memory, since this is 766 * the maximum mapped by the Linux kernel during initialization. 767 */ 768 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 769 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 770 771 #ifdef CONFIG_CMD_KGDB 772 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 773 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 774 #endif 775 776 /* 777 * Environment Configuration 778 */ 779 #define CONFIG_ROOTPATH "/opt/nfsroot" 780 #define CONFIG_BOOTFILE "uImage" 781 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 782 783 /* default location for tftp and bootm */ 784 #define CONFIG_LOADADDR 1000000 785 786 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 787 788 #define CONFIG_BAUDRATE 115200 789 790 #define __USB_PHY_TYPE utmi 791 792 /* 793 * T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be 794 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 795 * cacheline interleaving. It can be cacheline, page, bank, superbank. 796 * See doc/README.fsl-ddr for details. 797 */ 798 #ifdef CONFIG_PPC_T4240 799 #define CTRL_INTLV_PREFERED 3way_4KB 800 #else 801 #define CTRL_INTLV_PREFERED cacheline 802 #endif 803 804 #define CONFIG_EXTRA_ENV_SETTINGS \ 805 "hwconfig=fsl_ddr:" \ 806 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 807 "bank_intlv=auto;" \ 808 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 809 "netdev=eth0\0" \ 810 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 811 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 812 "tftpflash=tftpboot $loadaddr $uboot && " \ 813 "protect off $ubootaddr +$filesize && " \ 814 "erase $ubootaddr +$filesize && " \ 815 "cp.b $loadaddr $ubootaddr $filesize && " \ 816 "protect on $ubootaddr +$filesize && " \ 817 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 818 "consoledev=ttyS0\0" \ 819 "ramdiskaddr=2000000\0" \ 820 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 821 "fdtaddr=c00000\0" \ 822 "fdtfile=t4240qds/t4240qds.dtb\0" \ 823 "bdev=sda3\0" \ 824 "c=ffe\0" 825 826 /* For emulation this causes u-boot to jump to the start of the proof point 827 app code automatically */ 828 #define CONFIG_PROOF_POINTS \ 829 "setenv bootargs root=/dev/$bdev rw " \ 830 "console=$consoledev,$baudrate $othbootargs;" \ 831 "cpu 1 release 0x29000000 - - -;" \ 832 "cpu 2 release 0x29000000 - - -;" \ 833 "cpu 3 release 0x29000000 - - -;" \ 834 "cpu 4 release 0x29000000 - - -;" \ 835 "cpu 5 release 0x29000000 - - -;" \ 836 "cpu 6 release 0x29000000 - - -;" \ 837 "cpu 7 release 0x29000000 - - -;" \ 838 "go 0x29000000" 839 840 #define CONFIG_HVBOOT \ 841 "setenv bootargs config-addr=0x60000000; " \ 842 "bootm 0x01000000 - 0x00f00000" 843 844 #define CONFIG_ALU \ 845 "setenv bootargs root=/dev/$bdev rw " \ 846 "console=$consoledev,$baudrate $othbootargs;" \ 847 "cpu 1 release 0x01000000 - - -;" \ 848 "cpu 2 release 0x01000000 - - -;" \ 849 "cpu 3 release 0x01000000 - - -;" \ 850 "cpu 4 release 0x01000000 - - -;" \ 851 "cpu 5 release 0x01000000 - - -;" \ 852 "cpu 6 release 0x01000000 - - -;" \ 853 "cpu 7 release 0x01000000 - - -;" \ 854 "go 0x01000000" 855 856 #define CONFIG_LINUX \ 857 "setenv bootargs root=/dev/ram rw " \ 858 "console=$consoledev,$baudrate $othbootargs;" \ 859 "setenv ramdiskaddr 0x02000000;" \ 860 "setenv fdtaddr 0x00c00000;" \ 861 "setenv loadaddr 0x1000000;" \ 862 "bootm $loadaddr $ramdiskaddr $fdtaddr" 863 864 #define CONFIG_HDBOOT \ 865 "setenv bootargs root=/dev/$bdev rw " \ 866 "console=$consoledev,$baudrate $othbootargs;" \ 867 "tftp $loadaddr $bootfile;" \ 868 "tftp $fdtaddr $fdtfile;" \ 869 "bootm $loadaddr - $fdtaddr" 870 871 #define CONFIG_NFSBOOTCOMMAND \ 872 "setenv bootargs root=/dev/nfs rw " \ 873 "nfsroot=$serverip:$rootpath " \ 874 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 875 "console=$consoledev,$baudrate $othbootargs;" \ 876 "tftp $loadaddr $bootfile;" \ 877 "tftp $fdtaddr $fdtfile;" \ 878 "bootm $loadaddr - $fdtaddr" 879 880 #define CONFIG_RAMBOOTCOMMAND \ 881 "setenv bootargs root=/dev/ram rw " \ 882 "console=$consoledev,$baudrate $othbootargs;" \ 883 "tftp $ramdiskaddr $ramdiskfile;" \ 884 "tftp $loadaddr $bootfile;" \ 885 "tftp $fdtaddr $fdtfile;" \ 886 "bootm $loadaddr $ramdiskaddr $fdtaddr" 887 888 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 889 890 #ifdef CONFIG_SECURE_BOOT 891 #include <asm/fsl_secure_boot.h> 892 #endif 893 894 #endif /* __CONFIG_H */ 895